公开(公告)号：US09991295B2

公开(公告)日：2018-06-05

申请号：US14772677

申请日：2014-11-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Zuqiang Wang

IPC: H01L21/00 ,  H01L27/12 ,  H01L49/02 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L51/52 ,  H01L21/02 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L21/02043 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L27/124 ,  H01L27/127 ,  H01L27/3244 ,  H01L28/60 ,  H01L29/401 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78672 ,  H01L51/5215 ,  H01L2227/323

Abstract: An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (TFTs) and conductive electrodes; the TFT includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode. With improved layer structures of the array substrate, a plurality of layer structures is formed in one patterning process by stepped photoresist process, so as to reduce the frequency of patterning processes, better ensure the compactness of the array substrate, and guarantee good contact between the layer structures in the array substrate.

公开(公告)号：US09818775B2

公开(公告)日：2017-11-14

申请号：US15443028

申请日：2017-02-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jang Soon Im ,  Chien Hung Liu

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L27/1288 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

公开(公告)号：US09768308B2

公开(公告)日：2017-09-19

申请号：US14768349

申请日：2015-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong Lu ,  Zheng Liu ,  Liang Sun ,  Xiaolong Li ,  Chunping Long

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/285 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/78618 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/1222 ,  H01L27/1274 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

Abstract: A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S1: sequentially forming an active layer (3), a gate insulation layer (4), a gate electrode (5) and an interlayer insulation layer (6) on a base substrate (1); S2: forming a first metal thin film layer (8); S3: performing a hydrogenation treatment on the active layer (3) and the gate insulation layer (6); S4: forming a second metal thin film layer (7), the second metal thin film layer (7) being used for forming a source electrode and a drain electrode.

公开(公告)号：US09633844B2

公开(公告)日：2017-04-25

申请号：US13703122

申请日：2012-10-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xueyan Tian ,  Chunping Long ,  Jiangfeng Yao

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  H01L27/12 ,  H01L21/321

CPC classification number: H01L21/02675 ,  H01L21/02436 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/02686 ,  H01L21/32115 ,  H01L27/1285

Abstract: Embodiments of the present invention provide a method for forming a low temperature polysilicon thin film. The method for forming the low temperature polysilicon thin film can include: depositing a buffer layer and an amorphous silicon layer on a substrate in this order; heating the amorphous silicon layer; performing an excimer laser annealing process on the amorphous silicon layer to form a polysilicon layer; oxidizing partially the polysilicon layer so as to form an oxidation portion at an upper portion of the polysilicon layer; and removing the oxidation portion of the polysilicon layer to form a polysilicon thin film.

公开(公告)号：US20160268320A1

公开(公告)日：2016-09-15

申请号：US14772677

申请日：2014-11-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Zuqiang Wang

IPC: H01L27/12 ,  H01L29/40 ,  H01L29/49 ,  H01L49/02 ,  H01L51/52 ,  H01L29/786 ,  H01L29/45

CPC classification number: H01L27/1288 ,  H01L21/02043 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L27/124 ,  H01L27/127 ,  H01L27/3244 ,  H01L28/60 ,  H01L29/401 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78672 ,  H01L51/5215 ,  H01L2227/323

Abstract: An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (TFTs) and conductive electrodes; the TFT includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode. With improved layer structures of the array substrate, a plurality of layer structures is formed in one patterning process by stepped photoresist process, so as to reduce the frequency of patterning processes, better ensure the compactness of the array substrate, and guarantee good contact between the layer structures in the array substrate.

Abstract translation: 提供阵列基板，其制造方法和显示装置。 阵列基板包括薄膜晶体管（TFT）和导电电极; TFT包括栅电极，源电极，漏电极和有源层; 源电极和漏极布置在有源层的相同层和两端，并且至少直接部分地接触有源层的上表面或下表面; 并且导电电极直接设置在电极上。 通过改善阵列基板的层结构，通过阶梯式光刻胶工艺在一个图案化工艺中形成多个层结构，从而降低图案化工艺的频率，更好地确保阵列基板的紧凑性，并保证阵列基板之间的良好接触 阵列基板中的层结构。

公开(公告)号：US20160268319A1

公开(公告)日：2016-09-15

申请号：US14769891

申请日：2014-09-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yinan Liang ,  Zheng Liu ,  Zuqiang Wang ,  Xueyan Tian

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L27/1255 ,  H01L27/3262 ,  H01L2227/323

Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

Abstract translation: 本公开内容提供了一种低温多晶硅场效应TFT阵列基板及其制造方法和显示装置。 该方法：在一个光刻工艺中，使用阶梯式光刻胶工艺在衬底上同时形成多晶硅存储电容器的多晶硅有源层和下极板; 在多晶硅有源层和多晶硅储存电容器的下极板上形成栅极绝缘层; 在所述栅极绝缘层上形成金属层，并蚀刻所述金属层以形成与所述栅电极，源电极，漏电极以及与所述源电极和所述漏极连接的数据线连接的栅电极和栅极线; 依次形成钝化层，光致抗蚀剂层和像素电极层，并在一个光刻工艺中图案化钝化层，光致抗蚀剂层和像素电极层以形成层间绝缘层通孔和像素电极的图案; 在像素电极上形成像素定义层。 本公开可以减少低温多晶硅场效应晶体管阵列基板的光刻工艺的时间，提高产量并降低成本。

公开(公告)号：US20240281101A1

公开(公告)日：2024-08-22

申请号：US18636496

申请日：2024-04-16

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long

IPC: G06F3/044 ,  G06F3/041 ,  G09G3/3233

CPC classification number: G06F3/0446 ,  G06F3/0412 ,  G06F2203/04112 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842

Abstract: A touch structure, a touch display panel and an electronic apparatus are provided. The touch structure includes a first touch electrode extended along a first direction and a second touch electrode extended along a second direction; the first touch electrode includes first electrode main body portions in a first conductive layer and a first connection portion in a second conductive layer; the second touch electrode includes second electrode main body portions and a second connection portion in the first conductive layer; the first connection portion is overlapped with the second connection portion in a direction perpendicular to the first conductive layer; the first conductive layer includes first metal meshes formed by first metal lines. The touch structure also includes a dummy electrode in the second conductive layer. The dummy electrode is coupled with at least one of the first connection portion and the second connection portion.

公开(公告)号：US20240072039A1

公开(公告)日：2024-02-29

申请号：US17897302

申请日：2022-08-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yong Qiao ,  Xinyin Wu

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/027 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127

Abstract: Provided an electrostatic protection circuit. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. Orthographic projection(s) of a channel and/or a first electrode of the first transistor on a main surface of the array substrate is/are within an orthographic projection of the first signal line on the main surface of the array substrate.

公开(公告)号：US11837609B2

公开(公告)日：2023-12-05

申请号：US17889528

申请日：2022-08-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long

IPC: H01L27/12 ,  H01L27/02 ,  G02F1/1362 ,  G09G3/20

CPC classification number: H01L27/124 ,  G02F1/136286 ,  H01L27/0248 ,  G09G3/20 ,  G09G2330/04

Abstract: An Electro-Static Discharge (ESD) protection circuit including a Thin Film Transistor (TFT) arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.

公开(公告)号：US20230162639A1

公开(公告)日：2023-05-25

申请号：US18095166

申请日：2023-01-10

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE Technology Group Co., Ltd.

Inventor： Jianbo Xian ,  Chunping Long ,  Hui Li ,  Yong Qiao

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0809 ,  G09G2310/0286

Abstract: The present disclosure relates to a driving unit, including a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit includes first switching elements, configured to output a first signal to the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit includes one or more second switching elements, and at least one of the second switching elements is configured to output a second signal to the driving unit in response to the control signal. The driving control circuit is configured to output the control signal at a control signal output terminal. Each of the first switching elements and second switching elements includes a transistor. Control signal input terminals of the first switching elements are coupled to the control signal output terminal through a control signal input line having a ring structure.