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公开(公告)号：US08741752B2
公开(公告)日：2014-06-03
申请号：US13605144
申请日：2012-09-06
IPC分类号： H01L21/28
CPC分类号： H01L21/28 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L27/0207 , H01L29/78
摘要： A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.
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公开(公告)号：US20140070414A1
公开(公告)日：2014-03-13
申请号：US13608211
申请日：2012-09-10
IPC分类号： H01L21/283 , H01L29/49
CPC分类号： H01L21/823456 , H01L29/66545
摘要： Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
摘要翻译： 公开了具有不同栅极长度和制造方法的栅极结构。 该方法包括使用掩模的图案形成具有第一临界尺寸的第一栅极结构。 该方法还包括使用掩模的图案形成具有与第一栅极结构的第一临界尺寸不同的第二临界尺寸的第二栅极结构。
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公开(公告)号：US08637908B2
公开(公告)日：2014-01-28
申请号：US13188789
申请日：2011-07-22
CPC分类号： H01L21/28 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L27/0207 , H01L29/78
摘要： A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.
摘要翻译： 一种方法包括在衬底的暴露部分和设置在衬底上的栅极堆叠上沉积虚拟填充材料，去除虚拟填充材料的部分以暴露衬底的部分，在衬底的暴露部分上形成间隔材料层 ，虚拟填充材料和栅极堆叠，去除间隔物材料层的部分以暴露衬底和虚拟填充材料的部分，在间隔材料，衬底和栅极堆叠的暴露部分上沉积介电层 去除所述介电层的部分以暴露所述间隔物材料的部分，去除所述间隔物材料的暴露部分以暴露所述基底的部分并且限定所述电介质层中的至少一个腔，以及在所述至少一个腔中沉积导电材料 。
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公开(公告)号：US20140024219A1
公开(公告)日：2014-01-23
申请号：US13552992
申请日：2012-07-19
IPC分类号： H01L21/306
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144 , Y10T428/24802
摘要： At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.
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公开(公告)号：US08563225B2
公开(公告)日：2013-10-22
申请号：US12126245
申请日：2008-05-23
IPC分类号： G03F7/30
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.
摘要翻译： 提供了在与设备中形成的MTJ自对准的半导体器件中形成硬掩模的方法。 该方法包括以下步骤：在MTJ的磁性堆叠的上表面上形成硬掩模材料层; 在所述硬掩模材料层的上表面的至少一部分上形成抗反射涂层（ARC）层，所述ARC层被选择为通过湿法蚀刻可去除; 在所述ARC层的上表面的至少一部分上形成光致抗蚀剂层; 去除所述光致抗蚀剂层和所述ARC层的至少一部分，从而暴露所述硬掩模材料层的至少一部分; 蚀刻硬掩模材料层以去除硬掩模材料层的暴露部分; 并且在相同的处理步骤中执行湿条以去除ARC层和光致抗蚀剂层的剩余部分而不干扰磁性堆叠。
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36.发明申请公开(公告)号：US20130069183A1
公开(公告)日：2013-03-21
申请号：US13426845
申请日：2012-03-22
IPC分类号： H01L29/82
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic memory cell having a self-aligned hard mask for contact to a magnetic tunnel junction is provided. For example, a magnetic memory cell includes a magnetic storage element formed on a semiconductor substrate, and a hard mask that is self-aligned with the magnetic storage element. The hard mask includes a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element, an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, wherein the ARC layer is selected to be removable by a wet etch, and a photoresist layer formed on at least a portion of an upper surface of the ARC layer. The selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack.
摘要翻译： 提供具有用于与磁性隧道结接触的自对准硬掩模的磁存储单元。 例如，磁存储单元包括形成在半导体衬底上的磁存储元件和与磁存储元件自对准的硬掩模。 硬掩模包括形成在磁性存储元件中的磁性堆叠的上表面上的硬掩模材料层，形成在硬掩模材料层的上表面的至少一部分上的抗反射涂层（ARC）层， 其中所述ARC层被选择为通过湿蚀刻可去除，以及形成在所述ARC层的上表面的至少一部分上的光致抗蚀剂层。 通过湿蚀刻技术在相同的处理步骤中除去ARC层和光致抗蚀剂层的选定部分，而不会干扰磁性堆叠。
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公开(公告)号：US20120280250A1
公开(公告)日：2012-11-08
申请号：US13100589
申请日：2011-05-04
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
摘要翻译： 一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁 结构体。 在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。 还描述了通过上述方法形成的结构。
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38.发明申请Magnetically De-Coupling Magnetic Tunnel Junctions and Bit/Word Lines for Reducing Bit Selection Errors in Spin-Momentum Transfer Switching 有权磁耦合磁隧道结和位/字线，用于减少旋转动力转换切换中的位选择错误公开(公告)号：US20090237982A1
公开(公告)日：2009-09-24
申请号：US12052326
申请日：2008-03-20
IPC分类号： G11C11/16 , H01L21/4763
CPC分类号： H01L27/228 , G11C11/1659 , H01L43/08 , H01L2924/0002 , H01L2924/00
摘要： Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element.
摘要翻译： 介绍了磁场对磁记忆体进行屏蔽的技术。 根据本发明的方面，磁存储元件形成有至少一个电耦合到磁存储元件的导电段。 导电段的至少一部分被磁性衬垫包围。 磁性衬垫可操作以将由导电段流过的电流产生的磁场的至少一部分转移离开磁存储元件。
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公开(公告)号：US07550044B2
公开(公告)日：2009-06-23
申请号：US12099441
申请日：2008-04-08
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译： 提供了磁性器件制造技术。 一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。 在待图案化材料的至少一个表面上形成硬掩模结构。 硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。 基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。 硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。 材料被蚀刻。
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公开(公告)号：US20080220374A1
公开(公告)日：2008-09-11
申请号：US12125099
申请日：2008-05-22
IPC分类号： G03F7/26
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
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