公开(公告)号：US07515459B2

公开(公告)日：2009-04-07

申请号：US11315129

申请日：2005-12-23

申请人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

发明人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个 连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

公开(公告)号：US07453716B2

公开(公告)日：2008-11-18

申请号：US11238381

申请日：2005-09-29

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US20060256612A1

公开(公告)日：2006-11-16

申请号：US11303910

申请日：2005-12-19

申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

公开(公告)号：US20090225590A1

公开(公告)日：2009-09-10

申请号：US12453420

申请日：2009-05-11

申请人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

公开(公告)号：US20060291277A1

公开(公告)日：2006-12-28

申请号：US11315347

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

发明人： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.

公开(公告)号：US07012834B2

公开(公告)日：2006-03-14

申请号：US10829807

申请日：2004-04-22

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

公开(公告)号：US07986551B2

公开(公告)日：2011-07-26

申请号：US12690999

申请日：2010-01-21

申请人： Mu-hui Park ,  Beak-hyung Cho ,  Hyung-rok Oh

发明人： Mu-hui Park ,  Beak-hyung Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

摘要： In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

摘要翻译： 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。

公开(公告)号：US20100128516A1

公开(公告)日：2010-05-27

申请号：US12323583

申请日：2008-11-26

申请人： Beak-hyung Cho ,  Yong-seok Jeon ,  Hye-jin Kim

发明人： Beak-hyung Cho ,  Yong-seok Jeon ,  Hye-jin Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2213/72

摘要： A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.

摘要翻译： 存储器件包括其中具有多个行和列的非易失性存储器单元（例如，PRAM单元）的存储器阵列和电耦合到存储器阵列中的对应的第一多列存储器单元的第一多个局部位线。 还提供了响应于位线选择信号的第一多个位线选择电路。 第一多个位线放电电路电连接到第一多个局部位线中的相应的位线。 提供位线放电控制电路以在操作期间用等效的位线放电信号驱动第一多个位线放电电路，以从第一多个局部位线中的所选择的一个读取数据。

公开(公告)号：US07639558B2

公开(公告)日：2009-12-29

申请号：US11315347

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

发明人： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

IPC分类号： G11C8/08 ,  G11C8/14

CPC分类号： G11C11/5678 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.

摘要翻译： 相变存储器件具有字线驱动器布局，其允许减小器件的核心区域的尺寸。 一方面，相变存储器件包括共享字线的多个存储单元块和驱动该字线的多个字线驱动器。 每个字线驱动器包括用于对字线预充电的预充电装置和用于放电字线的放电装置，并且其中预充电装置和放电装置交替地位于多个存储单元块之间。

公开(公告)号：US20090122593A1

公开(公告)日：2009-05-14

申请号：US12292200

申请日：2008-11-13

申请人： Beak-hyung Cho ,  Kwang-ho Kim ,  Young-pil Kim

发明人： Beak-hyung Cho ,  Kwang-ho Kim ,  Young-pil Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078

摘要： A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.

摘要翻译： 一种用于存储器的写入驱动器电路，其包括响应于所施加的电流脉冲而在RESET状态电阻和SET状态电阻之间改变的相变存储器单元，所述写入驱动器电路包括写入电平电平调整单元，其被配置为从第一至第n 响应于SET状态电流电平信号，其中n是大于1的整数，并且被配置为响应于RESET状态电流信号确定RESET状态电流电平，并且写入电流输出单元 被配置为产生与由写入电平电平调整单元确定的SET状态电流电平或RESET状态电流电平对应的SET状态电流脉冲和RESET状态电流脉冲之一。