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公开(公告)号：US07994612B2
公开(公告)日：2011-08-09
申请号：US12106476
申请日：2008-04-21
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。
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公开(公告)号：US07915670B2
公开(公告)日：2011-03-29
申请号：US11778185
申请日：2007-07-16
IPC分类号： H01L29/78 , H01L21/336 , H01L29/76
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
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公开(公告)号：US07902625B2
公开(公告)日：2011-03-08
申请号：US12106557
申请日：2008-04-21
IPC分类号： H01L31/058
CPC分类号： H01L35/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A metal gate thermocouple is provided. The thermocouple is configured to measure local temperatures of a device. The thermocouple is a passive device which senses temperature using the thermoelectric principle that when two dissimilar electrically conductive materials are joined, an electrical potential (voltage) is developed between the two materials. The voltage between the materials varies with the temperature of the junction (joint) between the materials. The thermocouple device includes a first conductor comprising a first material formed over a thin oxide layer or a shallow trench isolation (STI) structure and a second conductor comprising a second material formed over the thin oxide layer or the STI structure. The second conductor overlaps with the first conductor to form a thermocouple junction or dimension at least more than an alignment tolerance. The first and second materials are chosen such that the thermocouple junction formed between them exhibits a non-zero Seebeck coefficient. A conductive film formed over the first conductor and the second conductor and a non-conductive void or film is formed over the thermocouple junction.
摘要翻译： 提供金属栅极热电偶。 热电偶被配置为测量设备的局部温度。 热电偶是使用热电原理感应温度的无源器件，当两种不同的导电材料接合时，两种材料之间产生电位（电压）。 材料之间的电压随着材料之间的接头（接头）的温度而变化。 热电偶装置包括第一导体，其包括在薄氧化物层或浅沟槽隔离（STI）结构上形成的第一材料，以及包括在薄氧化物层或STI结构上形成的第二材料的第二导体。 第二导体与第一导体重叠以形成至少大于对准公差的热电偶结或尺寸。 选择第一和第二材料使得它们之间形成的热电偶结点呈现非零塞贝克系数。 形成在第一导体和第二导体上的导电膜和不导电的空隙或膜形成在热电偶结上。
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34.发明授权Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions and an underlying floating well section 有权具有深沟槽隔离区域的集成电路器件，用于所有阱间和阱内隔离，并且与相邻器件扩散区域和下面的浮动阱部分之间的连接处共享接触公开(公告)号：US07902608B2
公开(公告)日：2011-03-08
申请号：US12473324
申请日：2009-05-28
IPC分类号： H01L29/772 , H01L21/70
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104
摘要： Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions used for intra-well isolation effectively create some floating well sections, which must each be connected to a supply voltage (e.g., Vdd) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact to a junction between the diffusion regions of adjacent devices and an underlying floating well section. This shared contact eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section.
摘要翻译： 公开了改进的集成电路器件结构（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）的实施例，以及形成使用DTI区域的结构的方法 从而提供了一种低成本的隔离方案，可避免由于STI-DTI失准导致的FET宽度变化。 此外，由于用于井内隔离的DTI区域有效地创建了一些浮动阱区段，其必须各自连接到电源电压（例如Vdd）以防止阈值电压（Vt）变化，所公开的集成电路器件还包括 与相邻设备的扩散区域和下面的浮动井段之间的连接处共享接触。 这种共享联系消除了如果每个浮动井段需要离散的电源电压接触将导致的成本和面积罚款。
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35.发明授权Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure 有权具有合并源极/漏极硅化物的鳍型场效应晶体管结构和形成结构的方法公开(公告)号：US07851865B2
公开(公告)日：2010-12-14
申请号：US11873521
申请日：2007-10-17
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料 （例如，金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。
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36.发明授权Method of forming a transistor having gate and body in direct self-aligned contact 失效形成具有直接自对准接触的门和体的晶体管的方法公开(公告)号：US07659155B2
公开(公告)日：2010-02-09
申请号：US11683470
申请日：2007-03-08
IPC分类号： H01L29/78
CPC分类号： H01L29/78615 , H01L29/783
摘要： A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body.
摘要翻译： 公开了一种具有直接接触门和体的晶体管及相关方法。 在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。 一种方法可以包括提供身体; 形成与身体的侧壁的至少一部分接触的牺牲层; 在所述至少一部分之外形成围绕所述主体的介电层; 去除牺牲层; 以及围绕所述主体形成所述门，使得所述门接触所述主体的侧壁的至少一部分。
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公开(公告)号：US20090260669A1
公开(公告)日：2009-10-22
申请号：US12106557
申请日：2008-04-21
IPC分类号： H01L35/02
CPC分类号： H01L35/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A metal gate thermocouple is provided. The thermocouple is configured to measure local temperatures of a device. The thermocouple is a passive device which senses temperature using the thermoelectric principle that when two dissimilar electrically conductive materials are joined, an electrical potential (voltage) is developed between the two materials. The voltage between the materials varies with the temperature of the junction (joint) between the materials. The thermocouple device includes a first conductor comprising a first material formed over a thin oxide layer or a shallow trench isolation (STI) structure and a second conductor comprising a second material formed over the thin oxide layer or the STI structure. The second conductor overlaps with the first conductor to form a thermocouple junction or dimension at least more than an alignment tolerance. The first and second materials are chosen such that the thermocouple junction formed between them exhibits a non-zero Seebeck coefficient. A conductive film formed over the first conductor and the second conductor and a non-conductive void or film is formed over the thermocouple junction.
摘要翻译： 提供金属栅极热电偶。 热电偶被配置为测量设备的局部温度。 热电偶是使用热电原理感应温度的无源器件，当两种不同的导电材料接合时，两种材料之间产生电位（电压）。 材料之间的电压随着材料之间的接头（接头）的温度而变化。 热电偶装置包括第一导体，其包括在薄氧化物层或浅沟槽隔离（STI）结构上形成的第一材料，以及包括在薄氧化物层或STI结构上形成的第二材料的第二导体。 第二导体与第一导体重叠以形成至少大于对准公差的热电偶结或尺寸。 选择第一和第二材料使得它们之间形成的热电偶结点呈现非零塞贝克系数。 形成在第一导体和第二导体上的导电膜和不导电的空隙或膜形成在热电偶结上。
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公开(公告)号：US20090121291A1
公开(公告)日：2009-05-14
申请号：US11939574
申请日：2007-11-14
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/0207 , H01L21/823412 , H01L29/785
摘要： Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.
摘要翻译： 公开了半导体结构的实施例以及形成半导体结构的方法，其同时使器件密度最大化并避免接触栅极间距和鳍片间距失配，当在衬底上的有限区域内形成多个平行的有角度的鳍片然后穿过多个平行 门（例如，在堆叠，人字形配置的CMOS设备的情况下）。 这是通过使用而不是最小光刻鳍间距来实现的，而是通过使用根据预先选择的接触栅间距，预选翅片角和预选择的周期性图案计算的鳍间距来实现 在有限的区域内相对于门定位翅片。 因此，所公开的结构和方法允许将具有给定区域中的多个堆叠的平面FET的半导体产品设计布局转换成具有多个，堆叠的，人造V形的非平面FET的半导体产品设计布局 区。
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公开(公告)号：US20090020830A1
公开(公告)日：2009-01-22
申请号：US11869145
申请日：2007-10-09
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译： 公开了用于非对称场效应晶体管结构的设计结构的实施例以及形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（ 即，以最小的电路延迟来提供改进的驱动电流）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。
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公开(公告)号：US07335932B2
公开(公告)日：2008-02-26
申请号：US10907745
申请日：2005-04-14
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78645 , H01L29/78648
摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.
摘要翻译： 半导体结构及其制造方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括 设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g） 接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区 在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。
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