公开(公告)号：US20070023756A1

公开(公告)日：2007-02-01

申请号：US11161213

申请日：2005-07-27

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak ,  BethAnn Rainey

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak ,  BethAnn Rainey

IPC分类号： H01L29/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.

摘要翻译： 场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。 优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。 优选地，SiGe层包含碳。 优选地，该对第一栅极结构基本上横向于第二栅极结构。 此外，该对第一栅极结构优选地被绝缘层封装。

公开(公告)号：US20060234456A1

公开(公告)日：2006-10-19

申请号：US11426623

申请日：2006-06-27

申请人： Brent Anderson ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/7887 ,  Y10S438/954

摘要： A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.

摘要翻译： 四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。 该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。

公开(公告)号：US20060097329A1

公开(公告)日：2006-05-11

申请号：US10904357

申请日：2004-11-05

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

摘要翻译： 翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。 该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。 通道扩展增加了鳍片的通道部分的电容。

公开(公告)号：US20060076623A1

公开(公告)日：2006-04-13

申请号：US11270708

申请日：2005-11-09

申请人： Brent Anderson ,  MeiKei Leong ,  Edward Nowak

发明人： Brent Anderson ,  MeiKei Leong ,  Edward Nowak

IPC分类号： H01L27/12 ,  H01L29/788

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/982

摘要： Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

公开(公告)号：US20050275045A1

公开(公告)日：2005-12-15

申请号：US10710007

申请日：2004-06-11

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7833 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7835 ,  H01L29/785

摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.

摘要翻译： 场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。 底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。 下层区域减少重叠电容，从而提高开关速度。 欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。 因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

公开(公告)号：US20080090361A1

公开(公告)日：2008-04-17

申请号：US11866435

申请日：2007-10-03

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.

摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

公开(公告)号：US20080036000A1

公开(公告)日：2008-02-14

申请号：US11876830

申请日：2007-10-23

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/665 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.

摘要翻译： 半导体结构及其制造方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括 设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g） 接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区 在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。

公开(公告)号：US20070187769A1

公开(公告)日：2007-08-16

申请号：US11276135

申请日：2006-02-15

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/337 ,  H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11

摘要： Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.

摘要翻译： 公开了包括具有多个FET的第一器件和具有至少一个FET的第二器件的结构的实施例。 第一器件下方的半导体层的第一部分的部分被掺杂并接触以形成后栅极。 第二器件下方的半导体层的第二部分保持未掺杂和未接触，并因此用作绝缘体。 尽管由于背栅电容而导致第一器件的性能下降，但是后栅导致需要精确Vt控制的诸如SRAM单元的器件的净增益。 相反，尽管由于不存在后门而导致第二器件中的边缘Vt控制，但由于缺少电容负载和增加的绝缘，导致高性能器件（如逻辑电路）的净增益。

公开(公告)号：US20070158762A1

公开(公告)日：2007-07-12

申请号：US11275513

申请日：2006-01-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

摘要翻译： 公开了平面和非平面场效应晶体管（FET）结构和形成结构的方法。 这些结构包括在源极/漏极桥两端连接的分段有源器件（例如，用于非平面晶体管的多个半导体鳍片或用于平面晶体管的多个半导体层部分）。 在源极/漏极桥之间的分段有源器件上图案化栅电极，使得栅极电极在段之间（即，半导体鳍片或部分之间）具有减小的长度。 源极/漏极接触器接地在源/漏极桥上，使得它们仅与具有减小的栅极长度的栅电极的那些部分相对。 这些FET结构可以被配置为同时使晶体管的密度最大化，从而使漏极功率最小化，并且将源极/漏极触点和栅极导体之间​​的寄生电容保持在预定值以下，这取决于性能和密度要求。

公开(公告)号：US20070158752A1

公开(公告)日：2007-07-12

申请号：US11275492

申请日：2006-01-10

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/94

CPC分类号： H01L29/7843 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer comprises tensile sections above digital logic n-type transistors, compressive sections above digital logic p-type transistors and additional tensile sections above SRAM cells and/or analog FETs. An amorphization ion-implant is performed to relax the strain over SRAM cell p-FETs and, thereby, eliminate variability and avoid p-FET performance degradation in the SRAM cells. Additionally, this ion-implant can relax the strain above both analog p-FETs and n-FETs and, thereby, eliminate variability and the coupling of the logic device process to the analog FETs and provide more predictable and well-controlled analog FETs.

摘要翻译： 公开了一种在相同芯片上执行数字电路和SRAM单元和/或模拟FET的良好性能和稳定性权衡的结构的半导体结构和相关方法。 具体地说，在数字电路和芯片上的其它器件上形成双应变层。 双应变层包括位于数字逻辑n型晶体管之上的拉伸部分，位于数字逻辑p型晶体管之上的压缩部分以及SRAM单元和/或模拟FET之上的附加拉伸部分。 执行非晶化离子注入以松弛SRAM单元p-FET上的应变，从而消除SRAM单元中的可变性并避免p-FET性能下降。 此外，该离子注入可以松弛模拟p-FET和n-FET两者之上的应变，从而消除逻辑器件工艺与模拟FET的可变性和耦合，并提供更可预测和良好控制的模拟FET。