公开(公告)号：US07027337B2

公开(公告)日：2006-04-11

申请号：US11035601

申请日：2005-01-14

申请人： Christopher S. Johnson ,  Brian Johnson

发明人： Christopher S. Johnson ,  Brian Johnson

IPC分类号： G11C7/00

CPC分类号： G11C7/1087 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227

摘要： A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

摘要翻译： 逻辑电路在动态随机存取存储器件中以低功率模式，高写延迟模式或高功率模式，低写延迟模式操作写接收器。 逻辑电路接收指示高功率，低写入等待时间模式是否已经被使能的第一信号，指示存储器装置中的行存储器单元是否有效的第二信号，指示存储器件 正在以断电模式操作，并且指示存储器装置中的读取发送器是否有效的第四信号。 只要存储器件中的一行存储器单元处于活动状态，存储器件没有在掉电模式下运行，则只要高功率，低写入延迟模式被使能，逻辑电路就保持写入接收器的电源， 读存储器中的发送器不起作用。

公开(公告)号：US20060045206A1

公开(公告)日：2006-03-02

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L27/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US20060044891A1

公开(公告)日：2006-03-02

申请号：US10931472

申请日：2004-08-31

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US06989496B2

公开(公告)日：2006-01-24

申请号：US10363748

申请日：2001-09-19

申请人： Kristopher L. Desrochers ,  Brian Johnson ,  Fakhri Karray ,  Otman Adam Basir ,  Vladimir Filippov

发明人： Kristopher L. Desrochers ,  Brian Johnson ,  Fakhri Karray ,  Otman Adam Basir ,  Vladimir Filippov

IPC分类号： B60R21/32 ,  G01G19/08

CPC分类号： B60R21/01516 ,  B60R21/01532 ,  B60R21/01554 ,  G01G19/4142

摘要： This invention describes an occupant size and weight detection device consisting of a combination of force/load sensors (1), a head position sensor (2, 3), a multidirectional acceleration sensor (5), and a seat position sensor (4) used to determine the weight of an occupant based on weight distribution, body angle and foot position. The goal of the invention is to determine the weight of an occupant who is sitting in the front seat of a vehicle that is subjected to the dynamic forces resulting from the vehicle moving. This technology can be used in applications such as automotive occupant weight and position sensing for use with safety devices such as airbags.

摘要翻译： 本发明描述了由使用力/负载传感器（1），头部位置传感器（2,3），多向加速度传感器（5）和座椅位置传感器（4）的组合组成的乘员大小和重量检测装置 根据体重分布，体角和脚位来确定乘员的体重。 本发明的目的是确定坐在车辆前排座椅上的乘客的重量，车辆的前座受到车辆移动所产生的动力。 该技术可用于诸如汽车乘员重量和位置感测等用于安全装置如安全气囊的应用中。

公开(公告)号：US20050288403A1

公开(公告)日：2005-12-29

申请号：US10516169

申请日：2003-05-27

申请人： Monica de la Cruz ,  Cindy Doumen ,  Klaus Keck-Antoine ,  Brian Johnson

发明人： Monica de la Cruz ,  Cindy Doumen ,  Klaus Keck-Antoine ,  Brian Johnson

IPC分类号： C08L23/12 ,  C08K5/13 ,  C08K5/3435 ,  C08K5/524 ,  C08L23/10 ,  C08L35/00 ,  D01F6/46 ,  C08K5/34

CPC分类号： C08K5/3435 ,  C08K5/13 ,  C08K5/524 ,  C08L23/10 ,  C08L35/00 ,  C08L2201/08 ,  C08L23/12 ,  C08L2666/04

摘要： A polypropylene composition comprises: (a) a first stabilising component consisting of 100 ppm or less based on the weight of the polypropylene of a phenolic antioxidant or a mixture of phenolic antioxidants; (b) a second stabilising component consisting of 500 to 1000 ppm based on the weight of the polypropylene of a phosphite antioxidant or a mixture of phosphite antioxidants; and optionally (c) a third stabilising component consisting of 100 ppm to 5000 ppm based on the weight of the polypropylene of a hindered amine light stabiliser or a mixture of such stabilisers. The polypropylene composition advantageously is in the form of fibres. A preferred phenolic antioxidant is 1,3,5-tris(4-tert-butyl-3-hydroxy-2,6 dimethylbenzyl)-1,3,5-triazine-2,4,6-(1H, 3H, 5H)-trione (Lowinox 1790). A preferred phosphite antioxidant is tris(2,4-di-t-butylphenyl) phosphite (Alkanox 240). A preferred optional hindered amine light stabiliser is dimethyl succinate polymer with 4-hydroxy-2,2,6,6-tetramethyl-1-piperidine (Lowilite 62).

摘要翻译： 聚丙烯组合物包含：（a）基于酚类抗氧化剂的聚丙烯或酚类抗氧化剂的混合物的重量为100ppm或更少的第一稳定组分; （b）基于亚磷酸酯抗氧化剂的聚丙烯或亚磷酸酯抗氧化剂的混合物的重量的500至1000ppm的第二稳定组分; 和任选地（c）由受阻胺光稳定剂的聚丙烯的重量或这种稳定剂的混合物的100ppm至5000ppm组成的第三稳定组分。 聚丙烯组合物有利地是纤维的形式。 优选的酚类抗氧化剂是1,3,5-三（4-叔丁基-3-羟基-2,6-二甲基苄基）-1,3,5-三嗪-2,4,6-（1H，3H，5H ）-trione（Lowinox 1790）。 优选的亚磷酸酯抗氧化剂是三（2,4-二叔丁基苯基）亚磷酸酯（Alkanox 240）。 优选的可选受阻胺光稳定剂是具有4-羟基-2,2,6,6-四甲基-1-哌啶（Lowilite 62）的琥珀酸二甲酯聚合物。

公开(公告)号：US06930955B2

公开(公告)日：2005-08-16

申请号：US10851081

申请日：2004-05-24

申请人： Brian Johnson ,  Brent Keeth ,  Feng Lin

发明人： Brian Johnson ,  Brent Keeth ,  Feng Lin

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C11/4076

摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.

摘要翻译： 一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。 在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。 一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。 内部读延迟值用于抵消DRAM电路的内部读延迟。 一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

公开(公告)号：US06894551B2

公开(公告)日：2005-05-17

申请号：US10656987

申请日：2003-09-05

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： G06F1/06 ,  H03H11/16

CPC分类号： G11C7/22 ,  G06F1/06 ,  G11C7/222 ,  H03K5/15013 ,  H03K2005/00286

摘要： Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A second clock divider is connected to an output port of the first logic gate. The second clock divider is for generating a second-phase clock signal from the first input clock signal. A second logic gate is connected to an output port of the second clock divider. A third clock divider is connected to an output port of the second logic gate. The third clock divider is for generating a third-phase clock signal from a second input clock signal.

公开(公告)号：US20050099103A1

公开(公告)日：2005-05-12

申请号：US10705037

申请日：2003-11-10

申请人： Brian Johnson

发明人： Brian Johnson

IPC分类号： A47B81/00 ,  E05B15/00 ,  E05B15/16 ,  E05B17/20 ,  E05B65/00 ,  E05B65/44 ,  E05C3/04

CPC分类号： E05B17/2019 ,  E05B15/0053 ,  E05B65/0071 ,  E05B65/44 ,  E05B2015/165 ,  E05C3/041 ,  Y10T16/61 ,  Y10T70/5097 ,  Y10T292/1083

摘要： The present invention is directed to a lock for a cabinet of the type wherein a door of the cabinet is movable through a frame of the cabinet. An exemplary lock of the present invention includes a first and second restraining member connected by a rod and rotatable around an axis of rotation between a first position wherein a cabinet member is trapped between the restraining members and the door can not move through the frame and a second position wherein the door is freely movable through the frame. The lock optionally includes a mounting member having a rod-retaining section and optionally one or more rotation locks and/or one or more rotation restraints. The restraining members are optionally sized and shaped to facilitate rotation between the first and second position while accommodating different sizes and specifications of cabinet types. The lock optionally includes one or more strengthening members and end extensions angled on one or both ends of the rod. In additional embodiments of the present invention, the lock includes at least one friction pad for contacting a cabinet member and an adjustable connection between the rod and at least one restraining member.

摘要翻译： 本发明涉及一种用于这种类型的机柜的锁，其中机柜的门可通过机柜的框架移动。 本发明的示例性锁具包括第一和第二限制构件，其通过杆连接并且可绕第一位置旋转，第一位置和第二限制构件之间的限制构件和门之间的柜构件不能移动通过框架， 第二位置，其中门可自由移动通过框架。 锁可选地包括具有杆保持部分和可选地一个或多个旋转锁和/或一个或多个旋转限制器的安装构件。 限制构件可选地尺寸和形状以便于容纳不同尺寸和规格的柜类型的第一和第二位置之间的旋转。 锁可选地包括一个或多个加强构件和在杆的一端或两端成角度的端部延伸部。 在本发明的另外的实施例中，锁包括至少一个用于接触柜构件的摩擦垫和杆与至少一个限制构件之间的可调连接。

公开(公告)号：US06776567B2

公开(公告)日：2004-08-17

申请号：US10404797

申请日：2003-04-01

申请人： Brian Johnson ,  Edward Ng ,  Justin Mauck ,  Edward R. Dykes ,  Joseph Arthur Kraus

发明人： Brian Johnson ,  Edward Ng ,  Justin Mauck ,  Edward R. Dykes ,  Joseph Arthur Kraus

IPC分类号： B65G4907

CPC分类号： H01L21/67259 ,  H01L21/67126 ,  Y10S414/135 ,  Y10S414/136 ,  Y10S414/139

摘要： In a first aspect, a valve/sensor assembly is provided that includes a door assembly. The door assembly has (1) a first position adapted to seal an opening of a chamber; (2) a second position adapted to allow at least a blade of a substrate handler to extend through the opening of the chamber; and (3) a mounting mechanism adapted to couple the door assembly to the chamber. The valve/sensor assembly also includes a sensor system having a transmitter and a receiver adapted to detect a presence of a substrate and to communicate through at least a portion of the door assembly. Systems, methods and computer program products are provided in accordance with this and other aspects.

摘要翻译： 在第一方面，提供一种包括门组件的阀/传感器组件。 门组件具有（1）适于密封腔室的开口的第一位置; （2）第二位置，其适于允许至少一个衬底处理器的刀片延伸通过所述腔室的开口; 和（3）适于将门组件连接到腔室的安装机构。 阀/传感器组件还包括具有发射器和接收器的传感器系统，该发射器和接收器适于检测衬底的存在并且通过门组件的至少一部分进行通信。 根据本方面和其他方面提供系统，方法和计算机程序产品。

公开(公告)号：US06697297B2

公开(公告)日：2004-02-24

申请号：US10230673

申请日：2002-08-29

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

摘要： A system and memory including a circuit for setting write latency and a write/valid indicator. Time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. A write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

摘要翻译： 包括用于设置写延迟的电路和写/有效指示符的系统和存储器。 时间裕度区域刚好在第一或前沿之后并且恰好在时钟信号的前导码的第二或后沿之后建立，使得等待时间设置将被发现是不可接受的，如果其引起写入使能信号在这些区域中的任一个中转变 。 写入/有效指示电路通过延迟时钟信号或写入使能信号并分别将它们的定时与未延迟写入使能信号或时钟信号的定时进行比较来创建起始和结束时间余量区域。