公开(公告)号：US07888198B1

公开(公告)日：2011-02-15

申请号：US09313659

申请日：1999-05-18

申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/823425 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

摘要： An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

摘要翻译： 提供了金属氧化物半导体晶体管中的改善的源极/漏极结结构以及用于制造该结的新颖方法。 该配置在外围区域中使用门双侧壁间隔物，并且在单元阵列区域中采用栅极单侧壁间隔物。 有利地形成双侧壁间隔物以抑制短沟道效应，防止电流泄漏，并降低薄层电阻。 用于在周边区域中形成第二间隔物的绝缘层保留在电池阵列区域中，并且在用于接触开口形成的层间绝缘层的蚀刻步骤期间用作蚀刻停止层，并且还用作硅化物形成步骤期间的阻挡层 。 结果，简化了所得装置的制造过程。

公开(公告)号：US20100148811A1

公开(公告)日：2010-06-17

申请号：US12654235

申请日：2009-12-15

申请人： Chang-Hyun Cho ,  Joonyeon Kim ,  Sang-Gu Kang ,  Sanghoon Lee

发明人： Chang-Hyun Cho ,  Joonyeon Kim ,  Sang-Gu Kang ,  Sanghoon Lee

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R1/07378

摘要： A probe card transmitting electrical test signals between a tester and a semiconductor device includes a main circuit board configured to receive and transmit electrical signals from the tester, an interface unit electrically connected to the main circuit board, the interface unit including a signal line and a signal connection terminal, and at least one probe unit connected to the interface unit, the probe unit being detachable and including a plurality of probe needles arranged in a pattern corresponding to a pattern of electrode pads of the semiconductor device.

摘要翻译： 在测试器和半导体器件之间传输电测试信号的探针卡包括：主电路板，被配置为接收和发送来自测试器的电信号，电连接到主电路板的接口单元，所述接口单元包括信号线和 信号连接端子和连接到接口单元的至少一个探针单元，探针单元可拆卸并且包括以对应于半导体器件的电极焊盘图案的图案布置的多个探针。

公开(公告)号：US07388243B2

公开(公告)日：2008-06-17

申请号：US11430036

申请日：2006-05-09

申请人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

发明人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC分类号： H01L27/108

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

摘要翻译： 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US07329918B2

公开(公告)日：2008-02-12

申请号：US11419710

申请日：2006-05-22

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Yong-Seok Ahn

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Yong-Seok Ahn

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10891 ,  H01L28/91

摘要： A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

摘要翻译： 根据本发明的实施例的半导体存储器件包括存储节点和电阻器。 根据本发明的一些实施例的制造半导体存储器件的方法包括在包括存储单元阵列区域和芯/周边区域的半导体衬底上形成层间绝缘层; 在其上形成第一蚀刻停止层; 形成在所述存储单元阵列区域上沿至少一个方向线性布置的多个接触插塞; 在所得结构上形成第一导电层; 在其上形成第二蚀刻停止层; 蚀刻所述第二蚀刻停止层和所述第一导电层并形成在至少一个方向上非线性地布置的着陆焊盘和电阻; 以及在其外侧表面的整个外表面上形成在着陆垫上露出的储存节点。

公开(公告)号：US07236850B2

公开(公告)日：2007-06-26

申请号：US10504369

申请日：2002-04-18

申请人： Mun-Sang Kim ,  Sung-Chul Kang ,  Chang-Hyun Cho ,  Hyun-Oh Shin ,  Jea-Sun Kim ,  Yo-Ha Hwang

发明人： Mun-Sang Kim ,  Sung-Chul Kang ,  Chang-Hyun Cho ,  Hyun-Oh Shin ,  Jea-Sun Kim ,  Yo-Ha Hwang

IPC分类号： G06F19/00

CPC分类号： B25J17/0208 ,  B25J9/1015 ,  B25J9/1633 ,  B25J9/1697 ,  B25J19/0091 ,  G05B2219/39527 ,  G05B2219/39577 ,  G05B2219/40557 ,  G05B2219/40609

摘要： A working robot, which is able to perform a required operation by locating a tool on a working position of a moving object, comprises a robot body moving with the object according to the movement of the object with more than one degree of freedom; an actuator mounted on a free end of the robot body and including a tool mounting unit, on which the tool is mounted, connected by a passive joint which reacts passively to small displacement of the object for locating the tool on the working position; and a control device for controlling the robot body, the actuator, and the tool.

摘要翻译： 能够通过将工具定位在移动物体的工作位置上而能够进行所需操作的工作机器人包括：机器人主体，根据物体的移动具有多于一个自由度; 安装在所述机器人主体的自由端上的致动器，并且包括工具安装单元，所述工具安装在所述工具安装单元上，所述工具安装单元通过被动接头连接，所述被动接头被动地反应所述物体的小位移以将所述工具定位在所述工作位置上 以及用于控制机器人主体，致动器和工具的控制装置。

公开(公告)号：US07074667B2

公开(公告)日：2006-07-11

申请号：US10843837

申请日：2004-05-11

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Yong-Seok Ahn

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Yong-Seok Ahn

IPC分类号： H01L21/8242

CPC分类号： H01L27/10897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10891 ,  H01L28/91

摘要： A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

摘要翻译： 根据本发明的实施例的半导体存储器件包括存储节点和电阻器。 根据本发明的一些实施例的制造半导体存储器件的方法包括在包括存储单元阵列区域和芯/周边区域的半导体衬底上形成层间绝缘层; 在其上形成第一蚀刻停止层; 形成在所述存储单元阵列区域上沿至少一个方向线性布置的多个接触插塞; 在所得结构上形成第一导电层; 在其上形成第二蚀刻停止层; 蚀刻所述第二蚀刻停止层和所述第一导电层并形成在至少一个方向上非线性地布置的着陆焊盘和电阻; 以及在其外侧表面的整个外表面上形成在着陆垫上露出的储存节点。

公开(公告)号：US07056786B2

公开(公告)日：2006-06-06

申请号：US10762380

申请日：2004-01-23

申请人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

发明人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC分类号： H01L21/8242

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

摘要翻译： 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US20060111810A1

公开(公告)日：2006-05-25

申请号：US10504369

申请日：2002-04-18

申请人： Mun-Sang Kim ,  Sung-Chul Kang ,  Chang-Hyun Cho ,  Hyun-Oh Shin ,  Jea-Sun Kim ,  Yo-Ha Hwang

发明人： Mun-Sang Kim ,  Sung-Chul Kang ,  Chang-Hyun Cho ,  Hyun-Oh Shin ,  Jea-Sun Kim ,  Yo-Ha Hwang

IPC分类号： G06F19/00

CPC分类号： B25J17/0208 ,  B25J9/1015 ,  B25J9/1633 ,  B25J9/1697 ,  B25J19/0091 ,  G05B2219/39527 ,  G05B2219/39577 ,  G05B2219/40557 ,  G05B2219/40609

摘要： A working robot, which is able to perform a required operation by locating a tool on a working position of a moving object, comprises a robot body moving with the object according to the movement of the object with more than one degree of freedom; an actuator mounted on a free end of the robot body and including a tool mounting unit, on which the tool is mounted, connected by a passive joint which reacts passively to small displacement of the object for locating the tool on the working position; and a control device for controlling the robot body, the actuator, and the tool.

摘要翻译： 能够通过将工具定位在移动物体的工作位置上而能够进行所需操作的工作机器人包括：机器人主体，根据物体的移动具有多于一个自由度; 安装在所述机器人主体的自由端上的致动器，并且包括工具安装单元，所述工具安装在所述工具安装单元上，所述工具安装单元通过被动接头连接，所述被动接头被动地反应所述物体的小位移以将所述工具定位在所述工作位置上 以及用于控制机器人主体，致动器和工具的控制装置。

公开(公告)号：US20050020086A1

公开(公告)日：2005-01-27

申请号：US10730996

申请日：2003-12-10

申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/311

CPC分类号： H01L29/66553 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

公开(公告)号：US06753227B2

公开(公告)日：2004-06-22

申请号：US10437881

申请日：2003-05-13

申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

IPC分类号： H01L21336

CPC分类号： H01L21/823807 ,  H01L21/28061 ,  H01L21/823892 ,  H01L29/4933

摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

摘要翻译： 提供一种制造MOS晶体管的方法。 根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。 因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。