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47 条记录 (耗时 0.031 秒)

    Charge-trap nonvolatile memory devices
    31.
    发明授权
    Charge-trap nonvolatile memory devices 有权
    充电陷阱非易失性存储器件

    公开(公告)号：US07772639B2

    公开(公告)日：2010-08-10

    申请号：US11700315

    申请日：2007-01-31

    申请人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

    发明人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

    摘要翻译： 提供包括半导体衬底上的器件隔离图案的非易失性存储器件。 器件隔离图案限定半导体衬底的单元有源区和外围有源区。 提供跨越电池有源区的电池栅电极。 在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。 在存储单元图形和单元有源区之间设置隧道绝缘膜。 本文还提供了制造非易失性存储器件的相关方法。

    Nonvolatile memory device having cell and peripheral regions and method of making the same
    32.
    发明申请
    Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
    具有单元和外围区域的非易失性存储器件及其制造方法

    公开(公告)号：US20080237700A1

    公开(公告)日：2008-10-02

    申请号：US12078143

    申请日：2008-03-27

    申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构 栅电极。 可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。 存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或 同时提供较低的电阻。

    Charge pump with balanced and constant up and down currents
    34.
    发明授权
    Charge pump with balanced and constant up and down currents 有权
    电荷泵具有平衡和恒定的上下电流

    公开(公告)号：US07256631B2

    公开(公告)日：2007-08-14

    申请号：US11188833

    申请日：2005-07-25

    申请人： Ju-Hyung Kim

    发明人： Ju-Hyung Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0895

    摘要： A charge pump generates a first sub up current and a second sub up current that vary complementarily with a change in a voltage at an output terminal. The charge pump also generates a first sub down current and a second sub down current that vary complementarily with the change in the voltage at the output terminal. With such complementary relationships, the total up/down currents remain substantially constant and balanced with the change in the voltage at the output terminal.

    摘要翻译： 电荷泵产生与输出端子处的电压变化互补地变化的第一次上升电流和第二次上升电流。 电荷泵还产生与输出端子处的电压变化互补地变化的第一次降压电流和第二次降压电流。 通过这种互补关系，总上升/下降电流保持基本恒定，并与输出端子电压的变化相平衡。

    Voltage-controlled oscillators with controlled operating range and related bias circuits and methods
    35.
    发明申请
    Voltage-controlled oscillators with controlled operating range and related bias circuits and methods 失效
    具有受控工作范围和相关偏置电路和方法的压控振荡器

    公开(公告)号：US20060033591A1

    公开(公告)日：2006-02-16

    申请号：US11198691

    申请日：2005-08-05

    申请人： Woo-Seok Kim ,  Ju-Hyung Kim

    发明人： Woo-Seok Kim ,  Ju-Hyung Kim

    IPC分类号： H03L7/099

    CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/2472 ,  H03L1/022 ,  H03L7/099

    摘要： A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.

    摘要翻译： 压控振荡器包括偏置电路和延迟电路。 偏置电路可以产生具有基于输入电压信号的电压电平并且受偏置电路中产生的最大电流信号和最小电流信号的值约束的电平的偏置电压信号对。 延迟电路产生具有响应于偏置电压信号对而变化的频率的输出信号。 由于压控振荡器VCO的工作频率范围由偏置电路限制，所以VCO可以以减小的增益进行工作，并且可以将最大工作频率限制在预定的水平。 VCO还可以包括偏置电路中的PTAT电流发生器，其可以允许VCO基于温度补偿VCO输出频率的变化。

    Nonvolatile memory device having cell and peripheral regions and method of making the same
    39.
    发明授权
    Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
    具有单元和外围区域的非易失性存储器件及其制造方法

    公开(公告)号：US07999307B2

    公开(公告)日：2011-08-16

    申请号：US12923998

    申请日：2010-10-20

    申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构 栅电极。 可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。 存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或 同时提供较低的电阻。