摘要:
Front-end radio frequency (RF) filters with embedded impedance transformation are disclosed. In an exemplary design, an apparatus includes an active circuit and an RF filter. The active circuit receives an input signal and provides an output signal. The RF filter is operatively coupled to an antenna and the active circuit and performs filtering for the input signal or output signal. The RF filter is impedance matched to the active circuit and includes a non-LC filter. In an exemplary design, the active circuit includes a low noise amplifier (LNA), and the RF filter includes a receive (RX) filter having an output impedance that is matched to an input impedance of the LNA. In another exemplary design, the active circuit includes a power amplifier, and the RF filter includes a transmit (TX) filter having an input impedance that is matched to an output impedance of the power amplifier.
摘要:
Compressed sensing is used to determine a model of a nonlinear system. In one example, L1-norm minimization is used to fit a generic model function to a set of samples thereby obtaining a fitted model. Convex optimization can be used to determine model coefficients that minimize the L1-norm. In one application, the fitted model is used to calibrate a predistorter. In another application, the fitted model function is used to predict future actions of the system. The generic model is made of up of constituent functions that may or may not be orthogonal to one another. In one example, an initial model function of non-orthogonal constituent functions is orthogonalized to generate a generic model function of constituent orthogonal functions. Although the number of samples to which the generic model is fitted can be less than the number of model coefficients, the fitted model nevertheless accurately models system nonlinearities.
摘要:
An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.
摘要:
Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift.
摘要:
Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal
摘要:
An adaptive filter suitable for fabrication on an RF integrated circuit and used for transmit (TX) leakage rejection in a wireless full-duplex communication system is described. The adaptive filter includes a summer and an adaptive estimator. The summer receives an input signal having a TX leakage signal and an estimator signal having an estimate of the TX leakage signal, subtracts the estimator signal from the input signal, and provides an output signal having the TX leakage signal attenuated. The adaptive estimator receives the output signal and a reference signal having a version of the transmit signal, estimates the TX leakage signal in the input signal based on the output signal and the reference signal, and provides the estimator signal. The adaptive estimator may utilize an LMS algorithm to minimize a mean square error between the TX leakage signal in the input signal and the TX leakage signal estimate in the estimator signal.
摘要:
Exemplary embodiments of the disclosure are directed to down-converting an RF signal of a transmitter to baseband, filtering the down-converted signal, and generating a composite signal based on the filtered down-converted signal and a transmission based-band signal.
摘要:
Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
摘要:
An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance.
摘要:
A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor. In accordance with the inventive teachings, the buffer has a low gain and high output impedance at first frequency (f1) of a first signal applied to the circuit and a second frequency (f2) of a second signal applied to the circuit and a unity gain and low output impedance a difference between the first and second frequencies. In another specific embodiment, the inductor is inserted between the output of the unity gain buffer and the input terminal of the transistor. In alternative embodiments, circuitry is shown for providing a direct current offset at the input of the transistor. As another alternative, the linearization circuit consists of series inductor and capacitor connected between the common and input terminals of the transistor. In yet another embodiment, the linearization circuit consists of the first and the second series inductor and capacitor circuits. The first series LC circuit is connected between the common terminal of the transistor and ground and the second series LC circuit is connected between the input terminal of the transistor and ground.