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公开(公告)号：US20120060905A1
公开(公告)日：2012-03-15
申请号：US12879209
申请日：2010-09-10
CPC分类号： H01L31/035227 , H01L31/022425 , H01L31/02363 , H01L31/02366 , H01L31/0352 , H01L31/1804 , Y02E10/50
摘要： A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
摘要翻译： 光电器件和方法包括在衬底层上沉积金属膜。 金属膜退火以在基底层上形成金属膜岛。 使用岛作为蚀刻掩模蚀刻衬底层，以在衬底层中形成柱。
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32.发明申请METHODS OF PREPARING FLEXIBLE PHOTOVOLTAIC DEVICES USING EPITAXIAL LIFTOFF, AND PRESERVING THE INTEGRITY OF GROWTH SUBSTRATES USED IN EPITAXIAL GROWTH 有权使用外延起绒制备柔性光伏器件的方法，并保持外延生长中使用的生长基质的一致性公开(公告)号：US20110186910A1
公开(公告)日：2011-08-04
申请号：US12878261
申请日：2010-09-09
IPC分类号： H01L29/06 , H01L21/302 , H01L31/0352
CPC分类号： H01L31/1892 , H01L21/7813 , H01L31/0735 , H01L31/1852 , H01L31/1896 , Y02E10/544
摘要： There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
摘要翻译： 公开了通过使用外延剥离来制造诸如柔性光伏（PV）器件的光敏器件的方法。 本文还描述了制备包含具有生长衬底的结构的柔性PV器件的方法，其中保护层的选择性蚀刻产生了适合于再利用的平滑生长衬底。
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公开(公告)号：US20120318338A1
公开(公告)日：2012-12-20
申请号：US13599577
申请日：2012-08-30
IPC分类号： H01L31/0236 , H01L31/076 , H01L31/075
CPC分类号： H01L31/1804 , H01L31/022425 , H01L31/02363 , H01L31/02366 , H01L31/0352 , H01L31/035227 , Y02E10/50
摘要： A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
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公开(公告)号：US20090095349A1
公开(公告)日：2009-04-16
申请号：US11869954
申请日：2007-10-10
申请人： Stephen R. Forrest , Guodan Wei , Kuen-Ting Shiu
发明人： Stephen R. Forrest , Guodan Wei , Kuen-Ting Shiu
IPC分类号： H01L31/0264 , H01L21/04
CPC分类号： B82Y30/00 , H01L31/03046 , H01L31/035281 , H01L31/0735 , Y02E10/544 , Y10S977/932 , Y10S977/948
摘要： A device comprises a plurality of fence layers of a semiconductor material and a plurality of alternating layers of quantum dots of a second semiconductor material embedded between and in direct contact with a third semiconductor material disposed in a stack between a p-type and n-type semiconductor material. Each quantum dot of the second semiconductor material and the third semiconductor material form a heterojunction having a type II band alignment. A method for fabricating such a device is also provided.
摘要翻译： 一种器件包括半导体材料的多个栅栏层和第二半导体材料的量子点的多个交替层，该第二半导体材料的第二半导体材料的交替层被嵌入在与p型和n型之间的堆叠中的第三半导体材料之间并直接接触 半导体材料。 第二半导体材料的每个量子点和第三半导体材料形成具有II型带对准的异质结。 还提供了一种用于制造这种装置的方法。
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公开(公告)号：US09231133B2
公开(公告)日：2016-01-05
申请号：US12879209
申请日：2010-09-10
IPC分类号： H01L21/00 , H01L31/0236
CPC分类号： H01L31/035227 , H01L31/022425 , H01L31/02363 , H01L31/02366 , H01L31/0352 , H01L31/1804 , Y02E10/50
摘要： A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
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公开(公告)号：US08835266B2
公开(公告)日：2014-09-16
申请号：US13085511
申请日：2011-04-13
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/417
CPC分类号： H01L29/66522 , H01L29/41783 , H01L29/66628 , H01L29/66636 , H01L29/7838 , H01L29/7848
摘要： The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.
摘要翻译： 本公开提供了掩埋沟道半导体结构，其中使用结晶湿蚀刻来定制形成多层衬底的蚀刻区域的轮廓，其包括位于掩埋半导体沟道材料层顶部的化合物半导体层。 在化合物半导体上使用结晶湿式蚀刻可以使形成多层基板的源极凹部区域和漏极凹陷区域的形状成为可能。 这允许控制栅极重叠/欠压。 此外，在化合物半导体上使用晶体湿式蚀刻可以独立控制下面的掩埋半导体沟道区的长度。
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37.发明授权Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge 有权使用n + Ge的低温金属诱导结晶降低了III-V MOSFET的S / D接触电阻公开(公告)号：US08536043B2
公开(公告)日：2013-09-17
申请号：US13017127
申请日：2011-01-31
申请人： Jeehwan Kim , Jin-Hong Park , Devendra Sadana , Kuen-Ting Shiu
发明人： Jeehwan Kim , Jin-Hong Park , Devendra Sadana , Kuen-Ting Shiu
IPC分类号： H01L21/28
CPC分类号： H01L29/20 , H01L21/26513 , H01L21/28575 , H01L29/0847 , H01L29/267 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.
摘要翻译： 本发明的实施例提供一种制造电接触的方法。 该方法包括提供化合物III-V族半导体材料的衬底，其具有与衬底的表面相邻的至少一个导电掺杂区域。 该方法还包括通过在衬底的表面上沉积锗的单晶层以至少部分地覆盖在至少一个导电掺杂区域上来将至少一个导电掺杂区域的电接触制造到该至少一个导电掺杂区域， 通过注入掺杂剂，在非晶锗层的暴露表面上形成金属层，并对具有上覆金属层的非晶锗层进行金属诱导结晶（MIC）工艺，将锗的晶体层分解成无定形锗层， 将无定形锗层转化为结晶锗层并激活注入的掺杂剂。 电接触可以是晶体管的源极或漏极接触。
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公开(公告)号：US07915521B2
公开(公告)日：2011-03-29
申请号：US11869954
申请日：2007-10-10
申请人： Stephen R. Forrest , Guodan Wei , Kuen-Ting Shiu
发明人： Stephen R. Forrest , Guodan Wei , Kuen-Ting Shiu
IPC分类号： H01L31/042 , H01L31/00 , H01L21/00
CPC分类号： B82Y30/00 , H01L31/03046 , H01L31/035281 , H01L31/0735 , Y02E10/544 , Y10S977/932 , Y10S977/948
摘要： A device comprises a plurality of fence layers of a semiconductor material and a plurality of alternating layers of quantum dots of a second semiconductor material embedded between and in direct contact with a third semiconductor material disposed in a stack between a p-type and n-type semiconductor material. Each quantum dot of the second semiconductor material and the third semiconductor material form a heterojunction having a type II band alignment. A method for fabricating such a device is also provided.
摘要翻译： 一种器件包括半导体材料的多个栅栏层和第二半导体材料的量子点的多个交替层，该第二半导体材料的第二半导体材料的交替层被嵌入在与p型和n型之间的堆叠中的第三半导体材料之间并直接接触 半导体材料。 第二半导体材料的每个量子点和第三半导体材料形成具有II型带对准的异质结。 还提供了一种用于制造这种装置的方法。
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公开(公告)号：US20070110357A1
公开(公告)日：2007-05-17
申请号：US11274873
申请日：2005-11-15
申请人： Stephen Forrest , Kuen-Ting Shiu , Shashank Agashe
发明人： Stephen Forrest , Kuen-Ting Shiu , Shashank Agashe
CPC分类号： G02B6/12004 , G02B6/1228 , G02B2006/12083 , G02B2006/12133 , H01L31/02327 , H01S5/026 , H01S5/0264 , H01S5/1014 , H01S5/1032 , H01S5/1064 , H01S5/3213 , H01S5/50
摘要： An asymmetric twin waveguide (ATG) structure with an integrated amplifier and detector fabricated in a single active waveguide layer is disclosed. The structure comprises an active waveguide layer formed on a passive waveguide layer. The active and passive waveguides have different effective indices of refraction such that a first mode of light is confined primarily to the active waveguide and a second mode of light is confined primarily to the passive waveguide in the area where the waveguides overlap.
摘要翻译： 公开了在单个有源波导层中制造的具有集成放大器和检测器的不对称双波导（ATG）结构。 该结构包括形成在无源波导层上的有源波导层。 有源和无源波导具有不同的有效折射率，使得第一模式主要被限制在有源波导上，并且第二光模式主要被限制在波导重叠的区域中的无源波导。
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公开(公告)号：US09105571B2
公开(公告)日：2015-08-11
申请号：US13368750
申请日：2012-02-08
申请人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
发明人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
IPC分类号： H01L21/24 , H01L21/225 , H01L21/285 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/20
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/20 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L2924/0002 , H01L2924/00
摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。
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