Systems, devices and methods using redundant error correction code bit storage
    32.
    发明授权
    Systems, devices and methods using redundant error correction code bit storage 有权
    使用冗余纠错码位存储的系统,设备和方法

    公开(公告)号:US08589767B2

    公开(公告)日:2013-11-19

    申请号:US12713853

    申请日:2010-02-26

    IPC分类号: G11C29/00

    CPC分类号: G06F11/1048 G11C2029/0411

    摘要: A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.

    摘要翻译: 诸如半导体存储器件的器件包括多个存储器单元,每个存储单元被配置为存储至少一个数据位和多个纠错码(ECC)单元,配置为冗余地存储用于存储器单元的ECC位。 根据一些实施例,多个ECC单元包括配置成存储ECC位及其补码的多对ECC单元。 根据另外的实施例,多个ECC小区包括被配置为存储ECC比特的相同副本的至少三个ECC小区的多个组。

    Resistive Memory Device and Test Systems and Methods for Testing the Same
    34.
    发明申请
    Resistive Memory Device and Test Systems and Methods for Testing the Same 有权
    电阻式存储器件和测试系统及其测试方法

    公开(公告)号:US20130051124A1

    公开(公告)日:2013-02-28

    申请号:US13587100

    申请日:2012-08-16

    IPC分类号: G11C11/00

    摘要: A resistive memory device and a system and method for testing the resistive memory device are provided. The resistive memory device includes a plurality of bit lines comprising at least one dummy bit line to which a plurality of resistive memory cells are connected, a conducting wire connected to the dummy bit line, a first switching element positioned between the dummy bit line and an external device outside the resistive memory device, and a second switching element positioned between the conducting wire and the external device. Accordingly, the operational reliability of the resistive memory device may be increased.

    摘要翻译: 提供了一种电阻式存储器件以及用于测试电阻式存储器件的系统和方法。 电阻式存储器件包括多个位线,其包括连接多个电阻存储器单元的至少一个虚拟位线,连接到虚拟位线的导线,位于虚拟位线和第二开关元件之间的第一开关元件 位于电阻性存储器件外的外部器件,以及位于导线和外部器件之间的第二开关元件。 因此,可以增加电阻式存储器件的操作可靠性。

    Resistive memory devices having a stacked structure and methods of operation thereof
    36.
    发明授权
    Resistive memory devices having a stacked structure and methods of operation thereof 有权
    具有堆叠结构的电阻式存储器件及其操作方法

    公开(公告)号:US08345464B2

    公开(公告)日:2013-01-01

    申请号:US12714950

    申请日:2010-03-01

    IPC分类号: G11C11/00

    摘要: A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.

    摘要翻译: 存储器件包括堆叠在半导体衬底上的多个电阻存储器单元层的堆叠电阻性存储单元阵列,其中相应的存储单元层被配置为根据包括每个单元的位数的各自的程序模式来存储数据。 该存储装置还包括控制电路,该控制电路被配置为响应于地址信号来识别所选择的存储器单元层的编程模式,并且根据所识别的程序模式响应于地址信号访问所选择的存储单元层。 程序模式可以包括单级单元模式和至少一个多级单元模式。

    SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE
    38.
    发明申请
    SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE 有权
    使用冗余错误修正代码位存储的系统,设备和方法

    公开(公告)号:US20100223532A1

    公开(公告)日:2010-09-02

    申请号:US12713853

    申请日:2010-02-26

    IPC分类号: H03M13/05 G06F11/10

    CPC分类号: G06F11/1048 G11C2029/0411

    摘要: A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.

    摘要翻译: 诸如半导体存储器件的器件包括多个存储器单元,每个存储单元被配置为存储至少一个数据位和多个纠错码(ECC)单元,配置为冗余地存储用于存储器单元的ECC位。 根据一些实施例,多个ECC单元包括配置成存储ECC位及其补码的多对ECC单元。 根据另外的实施例,多个ECC小区包括被配置为存储ECC比特的相同副本的至少三个ECC小区的多个组。

    Semiconductor memories with block-dedicated programmable latency register
    40.
    发明授权
    Semiconductor memories with block-dedicated programmable latency register 有权
    具有块专用可编程延迟寄存器的半导体存储器

    公开(公告)号:US07486575B2

    公开(公告)日:2009-02-03

    申请号:US11407024

    申请日:2006-04-20

    申请人: Chul Woo Park

    发明人: Chul Woo Park

    IPC分类号: G11C7/00

    摘要: An apparatus and method to delay output of data from different regions of a memory device in response to a read enable signal, the delaying of the output of data is based on the location of the regions of the memory device with respect to an output circuit that receives the data, wherein the different regions of the memory device have different CAS latency values dedicated to each region to set the delay time of each region of the memory device.

    摘要翻译: 响应于读使能信号延迟来自存储器件的不同区域的数据输出的装置和方法,数据输出的延迟是基于存储器件相对于输出电路的区域的位置, 接收数据,其中存储器件的不同区域具有专用于每个区域的不同CAS延迟值,以设置存储器件的每个区域的延迟时间。