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180 条记录 (耗时 0.03 秒)

    Strained channel transistor and methods of manufacture
    31.
    发明授权
    Strained channel transistor and methods of manufacture 有权
    应变通道晶体管及其制造方法

    公开(公告)号：US07052964B2

    公开(公告)日：2006-05-30

    申请号：US11081919

    申请日：2005-03-16

    申请人： Yee-Chia Yeo ,  Chih-Hsin Ko ,  Wen-Chin Lee ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Chih-Hsin Ko ,  Wen-Chin Lee ,  Chenming Hu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.

    摘要翻译： 半导体器件包括其中形成有第一和第二隔离沟槽的半导体材料区域。 第一隔离槽衬有具有低氧扩散速率的第一材料并填充绝缘材料。 第二隔离槽不是衬有第一材料，而是用绝缘材料填充。 形成在第一隔离区域附近的第一晶体管和与第二隔离区域相邻形成的第二晶体管。

    High performance semiconductor devices fabricated with strain-induced processes and methods for making same
    32.
    发明授权
    High performance semiconductor devices fabricated with strain-induced processes and methods for making same 有权
    用应变诱导工艺制造的高性能半导体器件及其制造方法

    公开(公告)号：US07394136B2

    公开(公告)日：2008-07-01

    申请号：US11194084

    申请日：2005-07-29

    申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

    发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

    摘要： A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

    摘要翻译： 公开了一种改进的驱动电流的高性能半导体器件及其制造方法。 半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。 在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。 在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。 然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

    High performance semiconductor devices fabricated with strain-induced processes and methods for making same
    34.
    发明授权
    High performance semiconductor devices fabricated with strain-induced processes and methods for making same 有权
    用应变诱导工艺制造的高性能半导体器件及其制造方法

    公开(公告)号：US06949443B2

    公开(公告)日：2005-09-27

    申请号：US10683901

    申请日：2003-10-10

    申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

    发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80

    CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

    摘要： A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

    摘要翻译： 公开了一种改进的驱动电流的高性能半导体器件及其制造方法。 半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。 在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。 在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。 然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

    Strained channel complementary field-effect transistors and methods of manufacture
    36.
    发明申请
    Strained channel complementary field-effect transistors and methods of manufacture 有权
    应变通道互补场效应晶体管及其制造方法

    公开(公告)号：US20050035470A1

    公开(公告)日：2005-02-17

    申请号：US10639170

    申请日：2003-08-12

    申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

    发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

    IPC分类号： H01L21/8238 ,  H01L27/088

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

    摘要： A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

    摘要翻译： 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

    Semiconductor device with high-k gate dielectric
    37.
    发明授权
    Semiconductor device with high-k gate dielectric 有权
    具有高k栅极电介质的半导体器件

    公开(公告)号：US07045847B2

    公开(公告)日：2006-05-16

    申请号：US10832020

    申请日：2004-04-26

    申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

    发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

    IPC分类号： H01L27/108

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

    摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

    Dual gate electrode metal oxide semciconductor transistors
    39.
    发明申请
    Dual gate electrode metal oxide semciconductor transistors 审中-公开
    双栅电极金属氧化物半导体晶体管

    公开(公告)号：US20070018259A1

    公开(公告)日：2007-01-25

    申请号：US11187271

    申请日：2005-07-21

    申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee

    发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823842 ,  H01L27/0922

    摘要： A semiconductor product includes a pair of field effect transistor device structures formed one each within a pair of doped well regions within a semiconductor substrate. The pair of field effect transistor device structures is formed with a pair of metal gate electrodes formed employing different laminated metal constructions. By correlating a work function within a metal layer within a gate electrode with a work function of a semiconductor substrate region over which it is formed, the field effect transistor devices are formed with enhanced performance.

    摘要翻译： 半导体产品包括在半导体衬底内的一对掺杂阱区域内形成的一对场效应晶体管器件结构。 一对场效应晶体管器件结构由一对使用不同层压金属结构形成的金属栅电极形成。 通过将栅电极内的金属层中的功函数与形成在其上的半导体衬底区域的功函数相关联，形成具有增强性能的场效应晶体管器件。