公开(公告)号：US5444411A

公开(公告)日：1995-08-22

申请号：US248350

申请日：1994-05-24

Applicant: Ming T. Yang ,  Chung-Cheng Wu

Inventor： Ming T. Yang ,  Chung-Cheng Wu

IPC: G06G7/14 ,  G06G7/42 ,  H03K17/62

CPC classification number: G06G7/14

Abstract: A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

Abstract translation: 使用电容器形成其输入的加权和的阈值电路使用两级电容器结构。 这两个阶段形成一个紧凑的结构，增加了可以处理的输入信号的数量，并增加了将权重分配给输入信号的灵活性。 用于输入信号的电容器电极被布置成两组，并且每组的电极被静电耦合到第一和第二电极。 分别从第一和第二电极延伸的第三和第四电极静电耦合到其电压相加的第五和第六电极的整体结构。 第五和第六电极导电地连接到FET阈值电路的栅极，其响应加权和相加的输入信号。

公开(公告)号：US5350700A

公开(公告)日：1994-09-27

申请号：US160243

申请日：1993-12-02

Applicant: Ming-Tzong Yang ,  Chung-Cheng Wu

Inventor： Ming-Tzong Yang ,  Chung-Cheng Wu

IPC: H01L21/331 ,  H01L21/74 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L21/74

Abstract: A method of fabricating a bipolar transistor with a buried subcollector by forming a collector layer and a base layer in a semiconductor substrate. A polysilicon layer is deposited over the base layer and spaced emitter and base contact regions formed in the base layer. A mask is formed over the emitter and base contact regions and the substrate anisotropically etched to form pedestals with vertical sidewalls. A masking layer is formed on the vertical sidewalls, and a large angle ion implant used to introduce ions beneath the collector layer, thereby forming a subcollector region.

Abstract translation: 一种通过在半导体衬底中形成集电极层和基极层来制造具有掩埋子集电极的双极晶体管的方法。 在基底层上沉积多晶硅层，并且在基底层中形成间隔开的发射极和基极接触区域。 在发射极和基极接触区域上形成掩模，并且各向异性蚀刻衬底以形成具有垂直侧壁的基座。 掩模层形成在垂直侧壁上，并且大角度离子注入用于将离子引入集电极层下面，从而形成子集电极区域。

公开(公告)号：US07399679B2

公开(公告)日：2008-07-15

申请号：US11288858

申请日：2005-11-29

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/337 ,  H01L21/336 ,  H01L21/76 ,  H01L21/425

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US07378889B2

公开(公告)日：2008-05-27

申请号：US11282585

申请日：2005-11-21

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H03K7/08

CPC classification number: H02M3/33507 ,  H02M2001/0032 ,  H03K3/00 ,  H03K17/00 ,  H03K17/0822 ,  Y02B70/16

Abstract: A pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit is used in a power supply. The present invention comprises a hysteresis comparison circuit extracting a feedback voltage, a high threshold voltage and a low threshold voltage, and the voltages are executed by a comparison and hysteresis operation to a output blanking signal, a PWM control unit extracting a detecting current signal and the feedback voltage to output a modulation signal after a comparison operation is executed; an OR gate circuit connected to the hysteresis comparison circuit and the PWM control unit for receiving the blanking signal and the modulation signal to output a reset signal; and a synchronization signal output unit connected to the OR gate circuit for receiving the reset signal and an oscillation signal to output the drive signal.

Abstract translation: 在电源中使用具有由输出电压反馈滞后电路控制的省电模式的脉宽调制装置。 本发明包括提取反馈电压，高阈值电压和低阈值电压的滞后比较电路，并且通过对输出消隐信号进行比较和滞后操作来执行电压，PWM控制单元提取检测电流信号，以及 在执行比较操作之后输出调制信号的反馈电压; 连接到迟滞比较电路的OR门电路和用于接收消隐信号和调制信号以输出复位信号的PWM控制单元; 以及连接到或门电路的同步信号输出单元，用于接收复位信号和振荡信号以输出驱动信号。

公开(公告)号：US07256569B2

公开(公告)日：2007-08-14

申请号：US11242915

申请日：2005-10-05

Applicant: Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

Inventor： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

IPC: G05F1/10 ,  G05F1/40 ,  H02H7/00

CPC classification number: G05F1/70

Abstract: The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

公开(公告)号：US20060109039A1

公开(公告)日：2006-05-25

申请号：US11282585

申请日：2005-11-21

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H03K3/017

CPC classification number: H02M3/33507 ,  H02M2001/0032 ,  H03K3/00 ,  H03K17/00 ,  H03K17/0822 ,  Y02B70/16

Abstract: A pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit is used in a power supply. The present invention comprises a hysteresis comparison circuit extracting a feedback voltage, a high threshold voltage and a low threshold voltage, and the voltages are executed by a comparison and hysteresis operation to a output blanking signal, a PWM control unit extracting a detecting current signal and the feedback voltage to output a modulation signal after a comparison operation is executed; an OR gate circuit connected to the hysteresis comparison circuit and the PWM control unit for receiving the blanking signal and the modulation signal to output a reset signal; and a synchronization signal output unit connected to the OR gate circuit for receiving the reset signal and an oscillation signal to output the drive signal.

Abstract translation: 在电源中使用具有由输出电压反馈滞后电路控制的省电模式的脉宽调制装置。 本发明包括提取反馈电压，高阈值电压和低阈值电压的滞后比较电路，并且通过对输出消隐信号进行比较和滞后操作来执行电压，PWM控制单元提取检测电流信号，以及 在执行比较操作之后输出调制信号的反馈电压; 连接到迟滞比较电路的OR门电路和用于接收消隐信号和调制信号以输出复位信号的PWM控制单元; 以及连接到或门电路的同步信号输出单元，用于接收复位信号和振荡信号以输出驱动信号。

公开(公告)号：US06406953B1

公开(公告)日：2002-06-18

申请号：US09053557

申请日：1998-04-01

Applicant: Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

Inventor： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC: H01L218238

CPC classification number: H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

Abstract translation: 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAMS和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US06284579B1

公开(公告)日：2001-09-04

申请号：US09418034

申请日：1999-10-14

Applicant: Jyh-Haur Wang ,  Bi-Ling Lin ,  Chung-Cheng Wu ,  Carlos H. Diaz

Inventor： Jyh-Haur Wang ,  Bi-Ling Lin ,  Chung-Cheng Wu ,  Carlos H. Diaz

IPC: H01L21338

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/7833

Abstract: A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

Abstract translation: 一种在微电子制造中采用的衬底内形成具有衰减漏极漏电流的场效应晶体管的方法。 提供了硅衬底，其中制造了使用砷（As）掺杂剂的具有轻掺杂n型漏极区（nLDD）的nMOS场效应晶体管（FET）。 然后将与In扩散结相邻的铟（In）掺杂剂原子注入到其中以形成p型凹穴。 然后避免了常规的高温快速热退火（RTA）步骤，并且替代地在750℃下进行2小时的热退火，随后注入的铟原子经历瞬时增强扩散（TED）以形成渐变连接轮廓，导致 衰减的漏极漏电流，并没有增加反向短沟道效应，从铟的强烈偏析到氧化硅。

公开(公告)号：US06248673B1

公开(公告)日：2001-06-19

申请号：US09511334

申请日：2000-02-23

Applicant: Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

Inventor： Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

IPC: H01L21469

CPC classification number: H01L29/518 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31629 ,  H01L21/324 ,  Y10S438/958

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device. The method is a “pure H2 (100%)” alloy recipe to use after contact opening or metal-1 formation.

Abstract translation: 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成微电子器件。 然后在微电子器件上形成由钝化介电材料形成的钝化介电层，该钝化介电材料选自氟硅酸盐玻璃（FSG）钝化介电材料，大气压化学气相沉积（APCVD）钝化介电材料，低于大气压的化学气相沉积 （SACVD）钝化介电材料和旋涂玻璃（SOG）钝化介电材料以从微电子器件形成钝化的微电子器件。 最后，在使用采用包含氢的气氛的热退火方法的同时进行退火，该钝化微电子器件形成稳定的钝化微电子器件。 该方法是在接触开口或金属-1形成之后使用的“纯H 2（100％）”合金配方。

公开(公告)号：US6144059A

公开(公告)日：2000-11-07

申请号：US375638

申请日：1999-08-17

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L27/108

CPC classification number: H01L28/84

Abstract: The present invention provides a process and a structure for increasing a capacitance of a stack capacitor. The process includes steps of: a) forming a contact hole on a silicon substrate having an oxide layer, b) forming a polysilicon contact plug of a first polysilicon layer in the contact hole; c) forming a second gibbous polysilicon layer on a surface of the contact plug, and d) forming a third polysilicon layer above the gibbous polysilicon layer and a portion of the oxide layer to form the stack capacitor, wherein the gibbous polysilicon layer increases the capacitance of the stack capacitor.