公开(公告)号：US08470700B2

公开(公告)日：2013-06-25

申请号：US12804487

申请日：2010-07-22

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

IPC分类号： H01L21/26

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66575

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

公开(公告)号：US20120228705A1

公开(公告)日：2012-09-13

申请号：US13046332

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层， 第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。 其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

公开(公告)号：US20120228695A1

公开(公告)日：2012-09-13

申请号：US13046313

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

公开(公告)号：US09034711B2

公开(公告)日：2015-05-19

申请号：US13046332

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层， 第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。 其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

公开(公告)号：US08896072B2

公开(公告)日：2014-11-25

申请号：US13736546

申请日：2013-01-08

申请人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

发明人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。 当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或倾斜的侧壁。 与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

公开(公告)号：US08889494B2

公开(公告)日：2014-11-18

申请号：US12980371

申请日：2010-12-29

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/78603

摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.

摘要翻译： 翅片型晶体管包括在衬底表面上的用于将晶体管的栅极与衬底隔离的介质层。 电介质层包括非选择性蚀刻的表面，以产生翅片结构的顶部，其具有减小横跨晶片的高度变化。 翅片型晶体管还可以包括至少低于S / D区的反掺杂区域，以减小寄生电容以改善其性能。

公开(公告)号：US08349692B2

公开(公告)日：2013-01-08

申请号：US13043323

申请日：2011-03-08

申请人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

发明人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。 当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或倾斜的侧壁。 与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

公开(公告)号：US20120228676A1

公开(公告)日：2012-09-13

申请号：US13043323

申请日：2011-03-08

申请人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

发明人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

摘要翻译： FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。 当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或成角度的侧壁。 与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

公开(公告)号：US20080150037A1

公开(公告)日：2008-06-26

申请号：US11615980

申请日：2006-12-24

申请人： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

发明人： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

IPC分类号： H01L27/092 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7846

摘要： A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

摘要翻译： 第一示例性实施例包括以下步骤和由其形成的结构。 在衬底内形成具有相对侧壁的沟槽。 在相对的沟槽侧壁上形成具有固有应力的应力层。 应力层在沟槽侧壁上具有应力层侧壁。 将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力 的应力层部分被松弛。

公开(公告)号：US07727856B2

公开(公告)日：2010-06-01

申请号：US11615980

申请日：2006-12-24

申请人： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

发明人： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

IPC分类号： H01L21/76

CPC分类号： H01L27/092 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7846

摘要： A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

摘要翻译： 第一示例性实施例包括以下步骤和由其形成的结构。 在衬底内形成具有相对侧壁的沟槽。 在相对的沟槽侧壁上形成具有固有应力的应力层。 应力层在沟槽侧壁上具有应力层侧壁。 将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力 的应力层部分被松弛。