公开(公告)号：US06900127B2

公开(公告)日：2005-05-31

申请号：US10649256

申请日：2003-08-27

申请人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Noel M. Russell

发明人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Noel M. Russell

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76862 ,  H01L21/76873

摘要： A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

摘要翻译： 沟槽（70）形成在电介质层（20）中。 使用物理气相沉积在沟槽中形成第一金属层（80）。 使用化学气相沉积在第一金属层（80）上的沟槽（70）中形成第二金属层（100）。 铜（110）用于通过将铜直接电镀到第二金属（100）上来填充沟槽（70）。

公开(公告)号：US08962374B2

公开(公告)日：2015-02-24

申请号：US13534037

申请日：2012-06-27

申请人： Satyavolu S. Papa Rao ,  Kathryn C. Fisher ,  Harold J. Hovel ,  Qiang Huang ,  Susan Huang ,  Young-Hee Kim

发明人： Satyavolu S. Papa Rao ,  Kathryn C. Fisher ,  Harold J. Hovel ,  Qiang Huang ,  Susan Huang ,  Young-Hee Kim

IPC分类号： H01L21/00

CPC分类号： H01L31/02168 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/52 ,  Y02E10/547 ,  Y02P70/521

摘要： A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.

公开(公告)号：US20120318341A1

公开(公告)日：2012-12-20

申请号：US13159897

申请日：2011-06-14

申请人： Kathryn C. Fisher ,  Qiang Huang ,  Satyavolu S. Papa Rao ,  David L. Rath

发明人： Kathryn C. Fisher ,  Qiang Huang ,  Satyavolu S. Papa Rao ,  David L. Rath

IPC分类号： H01L31/0216 ,  H01L31/18

CPC分类号： H01L31/02168 ,  H01L31/0201 ,  H01L31/0216 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/022433 ,  H01L31/18 ,  H01L31/1864 ,  Y02E10/50

摘要： Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided. In one embodiment, a method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate; forming a plurality of patterned antireflective coating layers on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger regions; forming a mask atop the plurality of patterned antireflective coating layers, the mask having a shape that mimics each patterned antireflective coating; electrodepositing a metal layer on the busbar region and the finger regions; removing the mask; and performing an anneal, wherein during the anneal metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy.

摘要翻译： 提供了其中前侧接触金属半导体合金金属化图案在边缘部分具有均匀厚度以及每个金属化图案的中心部分的光伏器件的制造方法。 在一个实施例中，提供了一种形成光伏器件的方法，该方法包括：pn结与p型半导体部分和n型半导体部分之间，其中一个半导体部分的上部暴露表面 表示半导体衬底的前侧表面; 在所述半导体表面的前侧表面上形成多个图案化的抗反射涂层，以提供包括汇流条区域和手指区域的网格图案; 在所述多个图案化的抗反射涂层之上形成掩模，所述掩模具有模仿每个图案化抗反射涂层的形状; 在母线区域和手指区域上电沉积金属层; 去除面膜; 并执行退火，其中在退火期间，来自金属层的金属原子与母线区域的半导体原子和形成金属半导体合金的指状区域反应。

公开(公告)号：US07939400B2

公开(公告)日：2011-05-10

申请号：US12235766

申请日：2008-09-23

申请人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

发明人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07485963B2

公开(公告)日：2009-02-03

申请号：US11614094

申请日：2006-12-21

申请人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

发明人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5329 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76852 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

摘要翻译： 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。

公开(公告)号：US07442597B2

公开(公告)日：2008-10-28

申请号：US11049275

申请日：2005-02-02

申请人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

发明人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US06919233B2

公开(公告)日：2005-07-19

申请号：US10335333

申请日：2002-12-31

申请人： Satyavolu S. Papa Rao ,  Asad M. Haider ,  Kelly Taylor ,  Ed Burke

发明人： Satyavolu S. Papa Rao ,  Asad M. Haider ,  Kelly Taylor ,  Ed Burke

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01L21/62

CPC分类号： H01L28/40 ,  H01L27/0805 ,  Y10T29/417

摘要： Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

摘要翻译： 描述了用于制造其的半导体器件及其制造方法，其中使用单个高k或铁电介质层来形成去耦电容器和模拟电容器段。 模拟电容器通过将模拟电容器段彼此串联耦合而形成，其中电容器段可以以相反的极性关系连接，从而为模拟电容器提供对称的性能特性。