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1.发明授权公开(公告)号：US07179747B2
公开(公告)日：2007-02-20
申请号：US10902243
申请日：2004-07-28
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/31116 , H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.
摘要翻译： 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。
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公开(公告)号：US07115467B2
公开(公告)日：2006-10-03
申请号：US10903712
申请日：2004-07-30
申请人： Sameer Kumar Ajmera , Darius L. Crenshaw , Stephan Grunow , Satyavolu S. Papa Rao , Phillip D. Matz
发明人： Sameer Kumar Ajmera , Darius L. Crenshaw , Stephan Grunow , Satyavolu S. Papa Rao , Phillip D. Matz
IPC分类号： H01L21/8242
CPC分类号： H01L28/75
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).
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3.发明授权公开(公告)号：US07485963B2
公开(公告)日：2009-02-03
申请号：US11614094
申请日：2006-12-21
IPC分类号： H01L23/48 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/76852 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.
摘要翻译： 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。
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公开(公告)号：US07256121B2
公开(公告)日：2007-08-14
申请号：US11002935
申请日：2004-12-02
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
摘要翻译： 本发明提供了一种在半导体衬底100上形成互连的方法。 该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。 势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。 蚀刻还去除了开口130底部的阻挡层230的至少一部分。
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公开(公告)号：US07148140B2
公开(公告)日：2006-12-12
申请号：US10901857
申请日：2004-07-28
IPC分类号： H10L21/44
CPC分类号： H01L21/76877 , H01L21/76883
摘要： A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).
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公开(公告)号：US06864108B1
公开(公告)日：2005-03-08
申请号：US10689218
申请日：2003-10-20
CPC分类号： G01K7/36 , G01K7/00 , H01L21/67248
摘要： A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10). The wafer is heated by a heat source (20) and the conductivity of the wafer (10) will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil (50) to change and the temperature of the wafer (10) can be determined by monitoring the inductance of the coil (50).
摘要翻译： 线圈（50）被放置成与半导体晶片（10）相邻。 使用AC激励电流来产生晶片（10）的变化的电磁场（60）。 晶片被热源（20）加热，并且晶片（10）的导电率将随晶片温度的变化而变化。 引起的涡流将导致线圈（50）的电感改变，并且可以通过监测线圈（50）的电感来确定晶片（10）的温度。
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公开(公告)号：US06900127B2
公开(公告)日：2005-05-31
申请号：US10649256
申请日：2003-08-27
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76862 , H01L21/76873
摘要： A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).
摘要翻译： 沟槽（70）形成在电介质层（20）中。 使用物理气相沉积在沟槽中形成第一金属层（80）。 使用化学气相沉积在第一金属层（80）上的沟槽（70）中形成第二金属层（100）。 铜（110）用于通过将铜直接电镀到第二金属（100）上来填充沟槽（70）。
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公开(公告)号：US07566627B2
公开(公告)日：2009-07-28
申请号：US11771298
申请日：2007-06-29
IPC分类号： H01L21/20
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.
摘要翻译： 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。
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9.发明申请公开(公告)号：US20090085197A1
公开(公告)日：2009-04-02
申请号：US11863477
申请日：2007-09-28
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
摘要翻译： 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。
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10.发明授权Single mask MIM capacitor and resistor with in trench copper drift barrier 有权单掩模MIM电容器和电阻器具有沟槽铜漂移屏障公开(公告)号：US07189615B2
公开(公告)日：2007-03-13
申请号：US11037530
申请日：2005-01-18
申请人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
发明人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76816 , H01L21/76849 , H01L23/5223 , H01L28/20 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
摘要翻译： 公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。 在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。 铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料， 的铜/底电极的沉积。 随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152） 还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。
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