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    Non-linear analog decision feedback equalizer
    31.
    发明授权
    Non-linear analog decision feedback equalizer 失效
    非线性模拟判决反馈均衡器

    公开(公告)号：US07983333B2

    公开(公告)日：2011-07-19

    申请号：US11730079

    申请日：2007-03-29

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H04H7/30

    CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

    Abstract: An equalizer is disclosed that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. The two symbols most commonly chosen to represent the two logic values taken on by binary symbols are binary zero and binary one. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. Likewise, when the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.

    Abstract translation: 公开了一种补偿由通信系统中的发射机，接收机和/或通信信道产生的非线性效应的均衡器。 非线性判决反馈均衡器通过基于先前接收到的符号在均衡系数之间进行选择来补偿对接收到的符号施加的非线性效应。 所接收的符号可以以基于二进制数系统的逻辑信号的形式表示。 最常选择用于表示由二进制符号取代的两个逻辑值的两个符号是二进制零和二进制。 当前一个接收到的符号是二进制零时，非线性判决反馈均衡器选择对应于二进制零的均衡系数来补偿被加载到接收符号上的非线性效应。 同样地，当前一个接收到的符号是二进制符号时，非线性判决反馈均衡器选择对应于二进制符号的均衡系数来补偿被加载到接收符号上的非线性效应。

    Low-jitter high-frequency clock channel
    32.
    发明授权
    Low-jitter high-frequency clock channel 有权
    低抖动高频时钟通道

    公开(公告)号：US07839161B2

    公开(公告)日：2010-11-23

    申请号：US12555564

    申请日：2009-09-08

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H03K17/16

    CPC classification number: G06F1/10

    Abstract: According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.

    Abstract translation: 根据一个一般方面，装置可以包括时钟信道，屏蔽隧道和时钟中继器。 在各种实施例中，时钟信道可以被配置为承载时钟信号，并且可以包括集成电路的金属层的一部分。 在一些实施例中，屏蔽隧道可以被配置为在至少四个方向上屏蔽来自其它信号的时钟信道，并且可以包括集成电路的至少三个金属层的部分。 屏蔽通道可以连接到正极和负极供电，以便为时钟转发器提供所需的电源。

    Digitally controlled threshold adjustment circuit
    35.
    发明申请
    Digitally controlled threshold adjustment circuit 失效
    数字控制阈值调节电路

    公开(公告)号：US20070241802A1

    公开(公告)日：2007-10-18

    申请号：US11731713

    申请日：2007-03-30

    Applicant: Namik Kocaman ,  Afshin Momtaz

    Inventor： Namik Kocaman ,  Afshin Momtaz

    IPC: H03L5/00

    CPC classification number: H03K5/151 ,  H03K5/003 ,  H03K5/086

    Abstract: Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first or the second component of the input signal. The example circuit also includes a power supply for providing a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.

    Abstract translation: 公开了阈值调整电路的实施例。 示例电路包括第一和第二薄氧化物晶体管的第一差分对。 第一和第二薄氧化物晶体管降低电路的输入信号的第一或第二分量的直流电压分量。 示例电路还包括第三和第四薄氧化物晶体管的第二差分对。 第二和第三薄氧化物晶体管增加输入信号的第一或第二分量的直流电压分量。 示例电路还包括用于向电路提供电源电压的电源，电源具有高于薄氧化物晶体管的可靠性水平的电压电平。 在示例电路中，通过使第一，第二，第三和第四薄氧化物晶体管中的每一个饱和的信号切换差分对薄氧化物晶体管中的每一个。

    Methods and circuitry for implementing first-in first-out structure
    38.
    发明授权
    Methods and circuitry for implementing first-in first-out structure 有权
    实现先进先出结构的方法和电路

    公开(公告)号：US07167024B2

    公开(公告)日：2007-01-23

    申请号：US11027864

    申请日：2004-12-31

    Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

    Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

    IPC: H03K19/173 ,  G11C11/00

    CPC classification number: G06F5/10 ,  G06F2205/106

    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

    Abstract translation: 用于实现高速先进先出（FIFO）结构的方法和电路。 在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。 在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。 公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

    Digitally controlled uniform step size CTF
    39.
    发明申请
    Digitally controlled uniform step size CTF 审中-公开
    数字控制均匀步长CTF

    公开(公告)号：US20060244519A1

    公开(公告)日：2006-11-02

    申请号：US11116160

    申请日：2005-04-27

    Applicant: Namik Kocaman ,  Afshin Momtaz

    Inventor： Namik Kocaman ,  Afshin Momtaz

    IPC: G01M11/00

    CPC classification number: H03F3/45183 ,  H03H11/1291

    Abstract: A continuous time filter having a first stage and a second stage. A first stage adjusts a bandwidth of the signal. A second stage adjusts bandwidth of the signal subsequent to the first stage. Each stage includes a first capacitor with a first capacitance and a second capacitor with a second capacitance for providing uniform step sizes for bandwidth adjustment. The continuous time filter may include a plurality of cascaded stages including the first stage and the second stage. In addition, a bandwidth adjustment across the first stage and the second stage may be controlled using a semi-interleaved thermometer coding to achieve a cascaded effect for the bandwidth adjustment.

    Abstract translation: 一种具有第一级和第二级的连续时间滤波器。 第一级调节信号的带宽。 第二级调整第一级之后的信号带宽。 每个级包括具有第一电容的第一电容器和具有第二电容的第二电容器，用于为带宽调整提供均匀的步长。 连续时间滤波器可以包括多个级联级，包括第一级和第二级。 此外，可以使用半交错温度计编码来控制跨第一级和第二级的带宽调整，以实现带宽调整的级联效应。

    Phase-locked loop circuit
    40.
    发明授权
    Phase-locked loop circuit 有权
    锁相环电路

    公开(公告)号：US07103130B2

    公开(公告)日：2006-09-05

    申请号：US11117768

    申请日：2005-04-28

    Applicant: Jun Cao ,  Afshin Momtaz

    Inventor： Jun Cao ,  Afshin Momtaz

    IPC: H03D3/24

    CPC classification number: H03L7/10 ,  H03L7/095 ,  Y10S331/02

    Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

    Abstract translation: 用于提高锁相环的精度和效率的方法和电路。 更具体地，本发明涉及一种用于监视两个信号之间的频率差异与至少一个数据信号的方法和装置，以便提高锁相环的精度和效率。 在本发明的一个实施例中，使用两个计数器来检查VCO信号和外部参考或输入信号之间的频率差。 提供可调阈值以确定两个信号的频率是否被认为处于频率锁定模式。 一对触发器用于通过验证频率差分检查的两个连续结果来最小化频率差异的任何错误检测。 另外，使用数据存在信号来控制锁相模式和锁频模式之间的转换，以最小化潜在的数据丢失。

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