公开(公告)号：US5077589A

公开(公告)日：1991-12-31

申请号：US666436

申请日：1991-03-11

申请人： Paige M. Holm ,  Daniel L. Rode

发明人： Paige M. Holm ,  Daniel L. Rode

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/812

CPC分类号： H01L29/402 ,  H01L29/7813 ,  H01L29/8122

摘要： A semiconductor device structure comprises a semiconductor substrate having a semiconductor layer of the same conductivity type formed on its first surface. A drain contact is formed on the second surface of the substrate and conductive regions having the opposite conductivity type of the substrate are formed in the semiconductor layer and are separated by a predetermined distance. Channel regions having the same conductivity type as the substrate are disposed above the conductive regions and source regions are disposed therein. A shielding region is then formed on the surface of the device structure in the area between the conductive regions. The structure allows for reduced or eliminated gate-drain capacitance, reduced output conductance and increased breakdown voltage capability.

摘要翻译： 半导体器件结构包括在其第一表面上形成有具有相同导电类型的半导体层的半导体衬底。 在衬底的第二表面上形成漏极接触，并且在半导体层中形成具有相反导电类型的衬底的导电区，并且隔开预定距离。 具有与衬底相同的导电类型的沟道区域设置在导电区域上方，并且源区域设置在其中。 然后在导电区域之间的区域中的器件结构的表面上形成屏蔽区域。 该结构允许降低或消除栅 - 漏电容，降低输出电导和提高击穿电压能力。

公开(公告)号：US09543067B2

公开(公告)日：2017-01-10

申请号：US14135956

申请日：2013-12-20

申请人： Carlos M. Acuna ,  Mohammad A. Faruque ,  Kevin R. Fugate ,  Todd D. Hoffmann ,  Paige M. Holm ,  Peter T. Jones ,  Rigoberto Lopez, Jr. ,  William D. McWhorter

发明人： Carlos M. Acuna ,  Mohammad A. Faruque ,  Kevin R. Fugate ,  Todd D. Hoffmann ,  Paige M. Holm ,  Peter T. Jones ,  Rigoberto Lopez, Jr. ,  William D. McWhorter

IPC分类号： G01R31/315 ,  H01F7/02 ,  G01R1/04

CPC分类号： H01F7/0294 ,  G01R1/0408 ,  G01R31/315

摘要： Methods, systems and apparatus are provided to apply a magnetic pre-conditioning to magnetic tunneling junction (MTJ) sensors and other micro-magnetic devices after fabrication but before testing, trimming or other subsequent processing. The fabricated sensor device is passed through a magnetic field that has a known direction and orientation relative to the device so that the device is placed into a known state prior to final testing and trimming. Various embodiments allow the field to be applied in situ by a permanent magnet or electromagnet as the devices are being processed by a conventional device handler or similar processing system.

摘要翻译： 提供了方法，系统和装置，用于在制造之后但在测试，修整或其它后续处理之前对磁性隧道结（MTJ）传感器和其它微型磁性装置施加磁性预处理。 制造的传感器装置通过具有相对于装置的已知方向和取向的磁场，使得装置在最终测试和修整之前被置于已知状态。 各种实施例允许现场通过永磁体或电磁体在现场施加，因为装置正在由传统的装置处理器或类似的处理系统处理。

公开(公告)号：US20140015123A1

公开(公告)日：2014-01-16

申请号：US13546902

申请日：2012-07-11

申请人： Philip H. Bowles ,  Paige M. Holm ,  Stephen R. Hooper ,  Raymond M. Roop

发明人： Philip H. Bowles ,  Paige M. Holm ,  Stephen R. Hooper ,  Raymond M. Roop

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L21/78

CPC分类号： B81B7/0006 ,  B81B7/0077 ,  B81B2201/02 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).

摘要翻译： 形成传感器封装（20）的方法（70）需要提供传感器晶片（74），传感器晶片（74）具有形成在位于通过接合周边（36）所描绘的区域（34）内的侧面（26）上的传感器（30），并且提供控制器 具有在一侧（38）处的控制电路（42）和在相对侧（40）上的接合周边（46）的晶片（82）。 控制器晶片（82）的接合周边（46）被接合到传感器晶片（74）的对应的接合周边（36），以形成其中控制电路（42）面向外的堆叠的晶片结构（48）。 锯切控制器晶片（82）以露出传感器晶片（74）上的接合焊盘（32），该接合焊盘引线键合到形成在晶片（82）的同一侧（38）上的对应接合焊盘（44） 电路（42）。 结构（48）被封装在包装材料（62）中，并被分割以产生传感器封装（20）。

公开(公告)号：US06809008B1

公开(公告)日：2004-10-26

申请号：US10652632

申请日：2003-08-28

申请人： Paige M. Holm ,  Jon J. Candelaria

发明人： Paige M. Holm ,  Jon J. Candelaria

IPC分类号： H01L2130

CPC分类号： H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

摘要： An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor wafer (300) having an interconnect via (505, 495, 485) substantially decoupled from the photosensing element (390), wherein the host (460) and donor (300) wafers are bonded through the optically active material in a region disposed near a metalization surface (450, 455, 445) of the CMOS layer (460) in order to allow fabrication of the interconnect (505, 495, 485). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated photosensing components that may be readily incorporated with existing technologies for the improvement of CMOS imaging, device package form factors, weights and/or other manufacturing, device or material performance metrics.

摘要翻译： 公开了一种用于提供适合于在CMOS成像应用中使用的集成光敏元件的示例性系统和方法，其特别包括：与单晶光学活性施主晶片（300）接合的经处理的CMOS主晶片（460）; 集成在所述光学活性施主晶片（300）中的光敏元件（390）具有与光敏元件（390）基本上分离的互连通孔（505,495,485），其中主体（460）和供体（300）晶片是 通过光学活性材料在设置在CMOS层（460）的金属化表面（450,455,445）附近的区域中，以便制造互连（505,495,485）。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改善或以其它方式优化光敏性能或其它材料特性。 本发明的示例性实施例代表性地提供了可以容易地与现有技术结合以用于改进CMOS成像，设备封装外形，重量和/或其它制造，器件或材料性能度量的集成光敏元件。

公开(公告)号：US5940683A

公开(公告)日：1999-08-17

申请号：US588470

申请日：1996-01-18

申请人： Paige M. Holm ,  Chan-Long Shieh ,  Curtis D. Moyer

发明人： Paige M. Holm ,  Chan-Long Shieh ,  Curtis D. Moyer

IPC分类号： H01L21/60 ,  G09F9/33 ,  H01L25/16 ,  H01L27/15 ,  H01L33/00 ,  H01L21/00

CPC分类号： H01L25/167 ,  G09F9/3026 ,  H01L25/162 ,  H01L27/156 ,  H01L2924/0002 ,  H01L33/0079

摘要： A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer. The light emitted from the LED display chip, being emitted through the remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer of the display chip.

摘要翻译： 一种制造发光二极管（LED）显示封装的发光二极管显示封装和方法，所述发光二极管（LED）显示封装包括形成在基板上的由阵列LED制成的LED阵列显示芯片，所述LED阵列显示芯片具有围绕所述LED阵列显示器周边定位的连接焊盘 芯片，具有连接到最上表面的连接焊盘的单独的硅驱动器芯片，定位成当使用晶片级处理技术正确地注册和互连时协作地接合显示芯片的那些。 显示芯片被倒装芯片安装到驱动器芯片上，并且具有位于由显示芯片和驱动器芯片限定的空间之间的芯片间接合电介质层。 LED显示器和驱动器芯片封装随后选择性地去除了最初形成LED阵列的衬底，从而暴露显示芯片的连接焊盘和剩余的铟 - 镓 - 铝 - 磷化物（InGaAlP）外延层。 从LED显示芯片发出的光通过显示芯片的剩余的铟镓铝磷化物（InGaAlP）外延层发射。

公开(公告)号：US5583350A

公开(公告)日：1996-12-10

申请号：US552155

申请日：1995-11-02

申请人： Michael P. Norman ,  Paige M. Holm

发明人： Michael P. Norman ,  Paige M. Holm

IPC分类号： G09F9/33 ,  H01L25/075 ,  H01L27/32 ,  H01L33/00 ,  H01L51/50

CPC分类号： H01L27/3225 ,  H01L25/0753 ,  H01L33/0025 ,  H01L51/5012 ,  H01L27/3209 ,  H01L27/3211 ,  H01L2924/0002

摘要： A full color light emitting diode display (310) utilizes semiconductor light emitting diodes (313) to produce red light and either organic or semiconductor light emitting diodes (312) to produce blue light. Green light is produced by either semiconductor light emitting diodes (313) or by organic light emitting diodes (343). An array of semiconductor light emitting diodes is formed on a semiconductor substrate (322) and an array of organic or semiconductor light emitting diodes is formed on an optically transparent substrate (311). The optically transparent and semiconductor substrates are attached together to form the multi-wavelength light emitting diode display (310).

摘要翻译： 全彩色发光二极管显示器（310）利用半导体发光二极管（313）产生红光，以及有机或半导体发光二极管（312）产生蓝光。 绿色光由半导体发光二极管（313）或有机发光二极管（343）产生。 在半导体衬底（322）上形成半导体发光二极管阵列，在光学透明衬底（311）上形成有机或半导体发光二极管阵列。 光学透明和半导体衬底附接在一起以形成多波长发光二极管显示器（310）。

公开(公告)号：US5237633A

公开(公告)日：1993-08-17

申请号：US791708

申请日：1991-11-14

申请人： Craig A. Gaw ,  Paige M. Holm ,  Kwong-Han H. Leung ,  George W. Rhyne ,  Daniel L. Rode

发明人： Craig A. Gaw ,  Paige M. Holm ,  Kwong-Han H. Leung ,  George W. Rhyne ,  Daniel L. Rode

IPC分类号： H04B10/12 ,  H05B33/08

CPC分类号： H05B33/0818 ,  H05B33/0803

摘要： A monolithic optoelectronic integrated circuit having an optical emission portion (18) and a drive portion (11, or 22 and 21). The drive portion is capable of accepting TTL and standard CMOS logic voltage levels. In a first embodiment, the monolithic optoelectronic integrated circuit (10) has a light emitting diode (18) driven by a dual gate FET (11). In a second embodiment, the monolithic optoelectronic integrated circuit (20) has a light emitting diode (18) driven by two FETs (22 and 21). In each embodiment (10 or 20), a gate (13 or 23) of the respective drive circuit accepts the TTL or standard CMOS logic voltage. Further, in each embodiment current limiting is accomplished by coupling a gate with the source of the FET (11 or 22). Thus, the output of the light emitting diode (18, 18) is controlled by an input signal to the drive circuit.

摘要翻译： 具有光发射部分（18）和驱动部分（11或22和21）的单片光电集成电路。 驱动部分能够接受TTL和标准CMOS逻辑电压电平。 在第一实施例中，单片光电集成电路（10）具有由双栅极FET（11）驱动的发光二极管（18）。 在第二实施例中，单片光电集成电路（20）具有由两个FET（22和21）驱动的发光二极管（18）。 在每个实施例（10或20）中，相应驱动电路的栅极（13或23）接受TTL或标准CMOS逻辑电压。 此外，在每个实施例中，通过将栅极与FET（11或22）的源耦合来实现电流限制。 因此，发光二极管（18,18）的输出由驱动电路的输入信号控制。

公开(公告)号：US4805003A

公开(公告)日：1989-02-14

申请号：US120569

申请日：1987-11-10

申请人： Paige M. Holm ,  Curtis D. Moyer

发明人： Paige M. Holm ,  Curtis D. Moyer

IPC分类号： H01L21/338 ,  H01L29/80 ,  H01L29/812 ,  H01L29/205

CPC分类号： H01L29/8122

摘要： A vertical III-V compound MESFET is provided. The MESFET has a buried P-type layer which separates the source and the drain regions. A small N-type region in the buried P layer connects the source channel to the drain area. This opening in the buried P layer is located underneath the Schottky gate.

摘要翻译： 提供垂直的III-V复合MESFET。 MESFET具有分离源区和漏区的掩埋P型层。 掩埋P层中的小N型区域将源极沟道连接到漏极区域。 掩埋P层中的这个开口位于肖特基门下方。