公开(公告)号：US20050023648A1

公开(公告)日：2005-02-03

申请号：US10822384

申请日：2004-04-12

申请人： Jin Jung ,  Hark-Moo Kim

发明人： Jin Jung ,  Hark-Moo Kim

IPC分类号： H01L21/66 ,  H01L21/30 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/822 ,  H01L23/52 ,  H01L23/544 ,  H01L27/04

CPC分类号： H01L23/544 ,  H01L21/3212 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Marking lines or patterns are formed among dummy patterns or on a reference plain of a semiconductor device requiring analysis to enable easy location of a point on the semiconductor device.

摘要翻译： 在虚拟图案之间或在需要分析的半导体器件的参考平面上形成标记线或图案，以便能够容易地在半导体器件上定位点。

公开(公告)号：US20070126054A1

公开(公告)日：2007-06-07

申请号：US11315295

申请日：2005-12-23

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234

摘要： A nonvolatile memory device that effectively prevents the occurrence of the hump phenomenon as well as a manufacturing method for fabricating the same, is presented. In one embodiment, the nonvolatile memory device includes an insulating spacer formed at interface between the active region and isolation layer, and a charge trapping dielectric layer that is formed in the active region between the neighboring two insulating spacers. The device also includes a gate electrode layer formed on the charge trapping dielectric layer and a source and drain formed in the active region at both sides of the gate electrode layer.

摘要翻译： 本发明提供一种有效地防止驼峰现象发生的非易失性存储装置及其制造方法。 在一个实施例中，非易失性存储器件包括在有源区和隔离层之间的界面处形成的绝缘隔离层，以及形成在相邻的两个绝缘间隔物之间​​的有源区中的电荷捕获电介质层。 该器件还包括形成在电荷捕获电介质层上的栅极电极层和形成在栅电极层两侧的有源区中的源极和漏极。

公开(公告)号：US20060268196A1

公开(公告)日：2006-11-30

申请号：US11442118

申请日：2006-05-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： G02F1/1335

CPC分类号： G02F1/133526

摘要： A liquid crystal panel includes a first substrate and a second substrate; a first electrode on a surface of the first substrate; a light refraction device on the second substrate, the light refraction device including a plurality of light refracting lenses facing the surface of the first substrate; and a liquid crystal layer interposed between the first electrode and the light refracting lenses.

摘要翻译： 液晶面板包括第一基板和第二基板; 在所述第一基板的表面上的第一电极; 在所述第二基板上的光折射装置，所述光折射装置包括面向所述第一基板的表面的多个光折射透镜; 以及插入在第一电极和光折射透镜之间的液晶层。

公开(公告)号：US20050247984A1

公开(公告)日：2005-11-10

申请号：US11129002

申请日：2005-05-13

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/66484 ,  H01L21/28052 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7831

摘要： A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of the semiconductor substrate.

摘要翻译： 公开了一种半导体器件及其制造方法，其中从主栅极到侧壁栅极形成一条线，使得可以将纳米级以上的晶体管缩放，并且半导体器件包括半导体衬底; 用于将半导体衬底分成场区域和有源区域的器件隔离层; 在半导体衬底的有源区的预定部分上的主栅极; 在半导体衬底上的主栅极的两侧的侧壁栅极; 主栅极和半导体衬底之间的主栅极绝缘层; 侧壁栅极和半导体衬底之间的侧壁栅极绝缘层; 在主栅极和侧壁栅极之间的绝缘中间层; 在主栅极和侧壁栅极的表面上的第一硅化物层，以将主栅极与侧壁栅极电连接; 以及在半导体衬底的有源区域中的侧壁栅极的两侧的源极和漏极区域。

公开(公告)号：US20050143964A1

公开(公告)日：2005-06-30

申请号：US10867783

申请日：2004-06-16

申请人： Joo Lee ,  Hyun Kim ,  Hyoung Kim ,  Jin Jung

发明人： Joo Lee ,  Hyun Kim ,  Hyoung Kim ,  Jin Jung

IPC分类号： G06T17/10 ,  G06F17/10 ,  G06T17/30

CPC分类号： G06T17/30

摘要： Disclosed is a method for designing a development drawing of a developable surface, the method including the steps of: setting a control contour from a circumference surface of a 3-dimensional model; performing an algorithm LIDM-GC-Dvlp to search a control point set; outputting a control point of a profile curve; visualizing a developable surface typed general circumference surface; modifying a design by a user depending on the visualized result; selecting a developable surface segment intended to generate the development drawing; and performing an algorithm LIDM-GC-Plane-Dvlp for the control point to generate the development drawing.

摘要翻译： 公开了一种用于设计可展开表面的显影图的方法，所述方法包括以下步骤：从三维模型的圆周表面设置控制轮廓; 执行算法LIDM-GC-Dvlp来搜索控制点集合; 输出轮廓曲线的控制点; 可视化表面类型的普通圆周表面; 根据可视化结果修改用户的设计; 选择用于生成开发图的可显影表面段; 并为控制点执行算法LIDM-GC-Plane-Dvlp以生成开发图。

公开(公告)号：US20050142751A1

公开(公告)日：2005-06-30

申请号：US11024832

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L21/8247 ,  G11C16/02 ,  H01L21/336 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526

摘要： Methods of fabricating a nonvolatile memory device are disclosed. A disclosed method comprises forming a first buffer oxide layer and a first buffer nitride layer on a semiconductor substrate; forming an opening through the first buffer nitride layer and the first buffer oxide layer; forming sidewall floating gates on sidewalls within the opening; forming a block oxide layer; forming a polysilicon main gate over the sidewall floating gates; forming first sidewall spacers on the sidewalls of the polysilicon main gate and the sidewall floating gates; forming common source and drain regions in the semiconductor substrate; filling the gap between the polysilicon main gates with an insulating layer; depositing a polysilicon layer for a word line; patterning a word line and the polysilicon main gate in the direction of a word line; and forming second sidewall spacers on the sidewalls of the word line and the polysilicon main gate.

摘要翻译： 公开了制造非易失性存储器件的方法。 所公开的方法包括在半导体衬底上形成第一缓冲氧化物层和第一缓冲氮化物层; 通过所述第一缓冲氮化物层和所述第一缓冲氧化物层形成开口; 在所述开口内的侧壁上形成侧壁浮动栅; 形成块状氧化物层; 在侧壁浮栅上形成多晶硅主栅极; 在多晶硅主栅极和侧壁浮动栅极的侧壁上形成第一侧壁间隔物; 在半导体衬底中形成公共源区和漏区; 用绝缘层填充多晶硅主栅之间的间隙; 为字线沉积多晶硅层; 在字线的方向上构图字线和多晶硅主栅; 以及在所述字线和所述多晶硅主栅极的侧壁上形成第二侧壁间隔物。

公开(公告)号：US20050142749A1

公开(公告)日：2005-06-30

申请号：US11024700

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  Y10S438/954

摘要： A flash memory and a flash memory fabrication method for increasing the coupling ratio by HSG including forming a STI region on a silicon substrate to define an active region, forming a tunneling oxide layer on the active region, and depositing an amorphous silicon layer on the silicon substrate. The method also includes patterning the amorphous silicon layer along a bit line direction, forming an embossed silicon layer including HSGs on the patterned amorphous silicon layer, and sequentially depositing an ONO layer and a polysilicon layer for a control gate on the resulting structure. The method further includes forming a photoresist pattern on the polysilicon layer, and forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along the bit line.

摘要翻译： 一种用于通过HSG增加耦合比的闪速存储器和闪速存储器制造方法，包括在硅衬底上形成STI区以限定有源区，在有源区上形成隧穿氧化物层，以及在硅上沉积非晶硅层 基质。 该方法还包括沿位线方向图案化非晶硅层，在图案化非晶硅层上形成包括HSG的压花硅层，并在所得结构上依次沉积ONO层和用于控制栅极的多晶硅层。 所述方法还包括在所述多晶硅层上形成光致抗蚀剂图案，以及通过使用所述光致抗蚀剂图案作为掩模蚀刻所述多晶硅层，并且沿着所述位线同时形成浮栅来形成控制栅极。

公开(公告)号：US20050142748A1

公开(公告)日：2005-06-30

申请号：US11024210

申请日：2004-12-27

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

摘要： Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.

摘要翻译： 公开了非易失性存储器件及其制造和驱动方法。 公开的装置和方法包括：在衬底上生长氧化物层并在氧化物层上沉积氮化物层; 图案化氮化物层; 在氮化物层的侧面上形成注入栅极; 依次在所得结构的表面上沉积第一多晶硅，电介质层和第二多晶硅; 图案化第二多晶硅，电介质层和第二多晶硅以形成栅电极; 去除喷射门之间的氮化物层; 通过执行离子注入工艺在每个栅极周围形成源极和漏极延伸区域; 在所述栅电极的侧面上形成侧壁间隔物; 以及通过用侧壁间隔物作为离子注入掩模进行离子注入工艺在衬底中形成源区和漏区。

公开(公告)号：US20050141286A1

公开(公告)日：2005-06-30

申请号：US11024628

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： G11C16/14 ,  G11C11/34 ,  G11C16/16 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C16/3468

摘要： An erase method in a flash memory device by which over-erase of the flash memory device is prevented. The method includes applying an electric field to a structure between the control gate and the semiconductor substrate by applying negative and positive voltages to the control gate and the semiconductor substrate, respectively. The method further includes weakening an intensity of the electric field applied to the tunnel oxide layer according to a progress of an erase time, and simultaneously, relatively strengthening an intensity of the electric field applied to the first and second block oxide layers to constantly maintain a prescribed quantity of electrons on a conduction band of the floating gate.

摘要翻译： 闪存装置中的擦除方法，通过该擦除方法防止闪速存储装置的过度擦除。 该方法包括分别通过向控制栅极和半导体衬底施加负电压和正电压来向控制栅极和半导体衬底之间的结构施加电场。 该方法还包括根据擦除时间的进行来减弱施加到隧道氧化物层的电场的强度，并且同时相对强化施加到第一和第二块状氧化物层的电场的强度，以恒定地维持 在浮栅的导带上规定量的电子。

公开(公告)号：US20050093054A1

公开(公告)日：2005-05-05

申请号：US10981164

申请日：2004-11-04

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/517 ,  H01L29/792

摘要： Non-volatile memory devices and methods of fabricating the same are disclosed. A disclosed non-volatile memory device includes: a tunnel oxide layer formed on a semiconductor substrate and having an energy bandgap; a storage oxide layer formed on the tunnel oxide layer and having an energy bandgap which is smaller than the energy bandgap of the tunnel oxide layer; a block oxide layer formed on the storage oxide layer and having an energy bandgap greater than the energy bandgap of the storage oxide layer; and a gate formed on the block oxide layer.

摘要翻译： 公开了非易失性存储器件及其制造方法。 所公开的非易失性存储器件包括：形成在半导体衬底上并具有能带隙的隧道氧化物层; 形成在所述隧道氧化物层上并且具有小于所述隧道氧化物层的能带隙的能带隙的存储氧化物层; 形成在所述存储氧化物层上并具有大于所述存储氧化物层的能带隙的能带隙的块状氧化物层; 以及形成在所述块状氧化物层上的栅极。