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92 条记录 (耗时 0.025 秒)

    Semiconductor device and method of fabricating the same
    31.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08592912B2

    公开(公告)日：2013-11-26

    申请号：US13106481

    申请日：2011-05-12

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.

    摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分， 以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度 。

    Semiconductor devices and methods of forming the same
    32.
    发明申请
    Semiconductor devices and methods of forming the same 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20100207184A1

    公开(公告)日：2010-08-19

    申请号：US12658154

    申请日：2010-02-03

    申请人： Kihyun Kim ,  Hansoo Kim ,  Wonseok Cho ,  Jinho Kim ,  Jaehoon Jang ,  Byoungkeun Son

    发明人： Kihyun Kim ,  Hansoo Kim ,  Wonseok Cho ,  Jinho Kim ,  Jaehoon Jang ,  Byoungkeun Son

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

    摘要： A semiconductor device includes insulating patterns and gate patterns alternately stacked on a substrate; an active pattern on the substrate, which extends upward along sidewalls of the insulating patterns and the gate patterns; data storage patterns interposed between the gate patterns and the active pattern; and a source/drain region disposed in the active pattern between a pair of gate patterns adjacent to each other.

    摘要翻译： 半导体器件包括交替层叠在衬底上的绝缘图案和栅极图案; 衬底上的有源图案，其沿绝缘图案和栅极图案的侧壁向上延伸; 插入在栅极图案和活动图案之间的数据存储图案; 以及设置在相互邻近的一对栅极图案之间的有源图案中的源极/漏极区域。

    Three-dimensional semiconductor memory device
    34.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08482138B2

    公开(公告)日：2013-07-09

    申请号：US13012485

    申请日：2011-01-24

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L29/40

    CPC分类号： H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

    摘要翻译： 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

    Methods of manufacturing three-dimensional semiconductor devices and related devices
    35.
    发明授权
    Methods of manufacturing three-dimensional semiconductor devices and related devices 有权
    制造三维半导体器件及相关器件的方法

    公开(公告)号：US08394716B2

    公开(公告)日：2013-03-12

    申请号：US12963241

    申请日：2010-12-08

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

    摘要翻译： 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    36.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    三维半导体器件及其制造方法

    公开(公告)号：US20110180941A1

    公开(公告)日：2011-07-28

    申请号：US13012485

    申请日：2011-01-24

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L23/52 ,  H01L21/28

    CPC分类号： H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

    摘要翻译： 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

    NONVOLATILE MEMORY DEVICES HAVING A THREE DIMENSIONAL STRUCTURE
    38.
    发明申请
    NONVOLATILE MEMORY DEVICES HAVING A THREE DIMENSIONAL STRUCTURE 有权
    具有三维结构的非易失性存储器件

    公开(公告)号：US20150076587A1

    公开(公告)日：2015-03-19

    申请号：US14548557

    申请日：2014-11-20

    申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

    摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

    摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

    PROGRAMMING METHODS FOR THREE-DIMENSIONAL MEMORY DEVICES HAVING MULTI-BIT PROGRAMMING, AND THREE-DIMENSIONAL MEMORY DEVICES PROGRAMMED THEREBY
    39.
    发明申请
    PROGRAMMING METHODS FOR THREE-DIMENSIONAL MEMORY DEVICES HAVING MULTI-BIT PROGRAMMING, AND THREE-DIMENSIONAL MEMORY DEVICES PROGRAMMED THEREBY 有权
    具有多位编程的三维存储器件的编程方法，以及编程的三维存储器件

    公开(公告)号：US20100322000A1

    公开(公告)日：2010-12-23

    申请号：US12818285

    申请日：2010-06-18

    申请人： Sunil Shim ,  Sunghoi Hur ,  Kihyun Kim ,  Hansoo Kim ,  Jaehun Jeong

    发明人： Sunil Shim ,  Sunghoi Hur ,  Kihyun Kim ,  Hansoo Kim ,  Jaehun Jeong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427

    摘要： In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

    摘要翻译： 在具有相对于衬底在水平和垂直方向上延伸的存储器单元阵列的三维存储器件的多位编程的方法中，该方法包括首先将要编程的存储器单元编程为第一组 状态。 然后，首先对与第一组状态中的一个相邻的要存储单元相邻的至少一个相邻存储单元进行编程。 在对所述至少一个相邻存储器单元进行第一编程之后，将要编程的存储器单元的第二编程为第二组状态之一，其中所述第二组状态具有大于所述状态数 第一套状态。