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    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    31.
    发明申请
    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
    片上高频电子放电装置的设计结构

    公开(公告)号：US20090316313A1

    公开(公告)日：2009-12-24

    申请号：US12144084

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H02H9/00 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

    摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。 每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。 所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

    SEMICONDUCTOR GROUND SHIELD
    35.
    发明申请
    SEMICONDUCTOR GROUND SHIELD 有权
    半导体接地屏蔽

    公开(公告)号：US20090146247A1

    公开(公告)日：2009-06-11

    申请号：US12371662

    申请日：2009-02-16

    申请人： Mete Erturk ,  Alvin J. Joseph ,  Anthony K. Stamper

    发明人： Mete Erturk ,  Alvin J. Joseph ,  Anthony K. Stamper

    IPC分类号： H01L29/70

    CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.

    摘要翻译： 公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。 接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。 接地屏蔽为第一金属（M1）级别提供低电阻，非常厚的金属，用于与标准后端（BEOL）集成结合的无源RF元件。 本发明还包括形成接地屏蔽的方法。

    Semiconductor ground shield method
    36.
    发明授权
    Semiconductor ground shield method 失效
    半导体接地屏蔽法

    公开(公告)号：US07501690B2

    公开(公告)日：2009-03-10

    申请号：US10908354

    申请日：2005-05-09

    申请人： Mete Erturk ,  Alvin J. Joseph ,  Anthony K. Stamper

    发明人： Mete Erturk ,  Alvin J. Joseph ,  Anthony K. Stamper

    IPC分类号： H01L29/70

    CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low sheet resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.

    摘要翻译： 公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。 接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。 接地屏蔽层为标准后端（BEOL）集成的无源RF元件提供了第一金属（M1）级别的低电阻，非常厚的金属。 本发明还包括形成接地屏蔽的方法。

    STRUCTURE FOR INTEGRATING AN RF SHIELD STRUCTURE IN A CARRIER SUBSTRATE
    37.
    发明申请
    STRUCTURE FOR INTEGRATING AN RF SHIELD STRUCTURE IN A CARRIER SUBSTRATE 审中-公开
    在载体基板上集成RF屏蔽结构的结构

    公开(公告)号：US20080116541A1

    公开(公告)日：2008-05-22

    申请号：US11561451

    申请日：2006-11-20

    申请人： Mete Erturk ,  Robert A. Groves ,  Anthony K. Stamper

    发明人： Mete Erturk ,  Robert A. Groves ,  Anthony K. Stamper

    IPC分类号： H01L23/552 ,  H01L21/02

    CPC分类号： H01L23/5225 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0224 ,  H01L2924/00

    摘要： A structure for shielding high frequency passive elements includes a first face of a semi-conductive substrate in parallel with a second face of a non-conductive substrate. The first face of the semi-conductive substrate is substantially parallel to a second face thereof. A passive element is disposed in the non-conductive substrate and is isolated from the second face of the non-conductive substrate. A plurality of conductive conduits disposed in the semi-conductive substrate extends from the first face to the second face thereof, each of the conduits isolated from one another by the semi-conductive substrate material and disposed substantially beneath the passive element. A ground plane disposed on the second face of the semi-conductive substrate electrically connects the conductive conduits disposed therein. An electrical connection between an electronic circuit in the semi-conductive substrate, the passive element and the ground plane holds the passive device and the ground plane at different potentials.

    摘要翻译： 用于屏蔽高频无源元件的结构包括与非导电衬底的第二面平行的半导电衬底的第一面。 半导体基板的第一面基本平行于其第二面。 无源元件设置在非导电衬底中，并且与非导电衬底的第二面隔离。 设置在半导电基板中的多个导电导管从第一面延伸到第二面，每个导管通过半导电基板材料彼此隔离并且基本上设置在无源元件的下方。 设置在半导电基板的第二面上的接地平面电连接设置在其中的导电导管。 半导体衬底中的电子电路，无源元件和接地平面之间的电连接将无源器件和接地平面保持在不同的电位。

    FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES
    38.
    发明申请
    FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES 有权
    制造POLYSILICON MOS器件和被动ESD器件

    公开(公告)号：US20140183753A1

    公开(公告)日：2014-07-03

    申请号：US13733243

    申请日：2013-01-03

    申请人： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H01L27/04 ,  H01L21/36

    CPC分类号： B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

    摘要： A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

    摘要翻译： 描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。 沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。 导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。 介电层沉积在导电层顶上，并且通孔形成在电介质层中。 另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。 另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。 然后通过排气孔去除上部和下部硅牺牲膜。