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公开(公告)号：US08842412B2
公开(公告)日：2014-09-23
申请号：US14176460
申请日：2014-02-10
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
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公开(公告)号：US20120275080A1
公开(公告)日：2012-11-01
申请号：US13096850
申请日：2011-04-28
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
摘要翻译： 描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。 描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。
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3.发明授权Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture 有权免费金属绝缘体金属（MIM）电容器和制造方法公开(公告)号：US08191217B2
公开(公告)日：2012-06-05
申请号：US12535769
申请日：2009-08-05
IPC分类号： H01G7/00
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/232 , H01G4/38 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , Y10T29/43 , Y10T29/435 , Y10T29/49156 , H01L2924/00
摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
摘要翻译： 同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。 该方法包括在电介质材料上沉积底板; 在底板上沉积低k介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器 第一厚度。
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4.发明授权Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture 有权免费金属绝缘体金属（MIM）电容器和制造方法公开(公告)号：US09424992B2
公开(公告)日：2016-08-23
申请号：US13427216
申请日：2012-03-22
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/232 , H01G4/38 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , Y10T29/43 , Y10T29/435 , Y10T29/49156 , H01L2924/00
摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
摘要翻译： 同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。 该方法包括在电介质材料上沉积底板; 在底板上沉积低k电介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器 第一厚度。
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5.发明申请COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE 有权合金金属绝缘子金属（MIM）电容器及其制造方法公开(公告)号：US20110032660A1
公开(公告)日：2011-02-10
申请号：US12535804
申请日：2009-08-05
CPC分类号： H01G4/06 , H01G4/1209 , H01G4/232 , H01G4/33 , H01L23/5223 , H01L27/016 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T29/417 , Y10T29/43 , Y10T29/435 , Y10T29/49156 , H01L2924/00
摘要： A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
摘要翻译： 提供了低电容密度，高电压MIM电容器和高密度MIM电容器及其制造方法。 该方法包括沉积彼此交错的多个板和多个电介质层。 该方法还包括蚀刻多个板的最上面板的一部分，同时保护最上面的板的其它部分。 最上层的受保护的其它部分形成第一金属 - 绝缘体 - 金属（MIM）电容器的顶板，并且蚀刻暴露第二MIM电容器的顶板。
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6.发明申请COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE 有权合金金属绝缘子金属（MIM）电容器及其制造方法公开(公告)号：US20110032659A1
公开(公告)日：2011-02-10
申请号：US12535769
申请日：2009-08-05
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/232 , H01G4/38 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , Y10T29/43 , Y10T29/435 , Y10T29/49156 , H01L2924/00
摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
摘要翻译： 同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。 该方法包括在电介质材料上沉积底板; 在底板上沉积低k电介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器 第一厚度。
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7.发明授权Planar cavity MEMS and related structures, methods of manufacture and design structures 有权平面腔MEMS及相关结构，制造方法和设计结构公开(公告)号：US08865497B2
公开(公告)日：2014-10-21
申请号：US12973422
申请日：2010-12-20
申请人： George A. Dunbar, III , Zhong-Xiang He , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
发明人： George A. Dunbar, III , Zhong-Xiang He , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.
摘要翻译： 形成至少一个微机电系统（MEMS）的方法包括在基板上形成下布线层。 该方法还包括从下布线层形成多条分立布线。 该方法还包括在多个离散导线上形成电极束。 形成电极束和多个离散导线中的至少一个形成有最小化后续硅沉积中的小丘和三点的布局。
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8.发明授权公开(公告)号：US08791545B2
公开(公告)日：2014-07-29
申请号：US13560446
申请日：2012-07-27
IPC分类号： H01L21/02
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。
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公开(公告)号：US20120070979A1
公开(公告)日：2012-03-22
申请号：US12887737
申请日：2010-09-22
IPC分类号： H01L21/768 , C25D5/12 , C25D5/14 , H01L21/02
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译： 本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。 电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。
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10.发明授权公开(公告)号：US07915158B2
公开(公告)日：2011-03-29
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.
摘要翻译： 描述形成片上高频静电放电装置的方法。 在一个实施例中，提供具有多金属层布线的晶片。 该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到 在第二介电层中分别有一个以上的电极。 多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。 至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。 在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。
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