公开(公告)号：US20090322920A1

公开(公告)日：2009-12-31

申请号：US12461950

申请日：2009-08-28

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: H04N5/335

CPC classification number: H04N5/361 ,  H04N5/235 ,  H04N5/243

Abstract: The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.

公开(公告)号：US07554870B2

公开(公告)日：2009-06-30

申请号：US12018860

申请日：2008-01-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of the columns is crossed by a bit line; a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer coupling its corresponding sense amplifier to its corresponding four bit lines.

Abstract translation: 在一个实施例中，提供了动态随机存取存储器（DRAM），其包括：多行存储器单元，每个存储单元行被排列成列，其中每个存储单元行被四行 字线，并且其中每个列被位线交叉; 对应于位线的多个读出放大器，使得单个读出放大器对应于每四位位线; 以及对应于多个读出放大器的多个4：1复用器，每个4：1多路复用器将其对应的读出放大器耦合到其对应的四位线。

公开(公告)号：US20080259705A1

公开(公告)日：2008-10-23

申请号：US12122932

申请日：2008-05-19

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C29/00

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件元件的可编程保险丝与多个存储器单元一起被使用以指示至少一个存储器单元不可用并且应该被移出而不工作。 软件可编程元件包括可编程寄存器，其适于移位指示至少一个存储器单元有缺陷的适当值。 硬件元件包括一个带可编程寄存器的保险丝。 移位由软件可编程保险丝或硬保险丝指示。 软熔丝寄存器可以链接在一起形成移位寄存器。

公开(公告)号：US07411847B2

公开(公告)日：2008-08-12

申请号：US11041829

申请日：2005-01-24

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C7/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/2602

Abstract: The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines for the lowest address are enabled. A voltage drop between neighboring wordlines and bitlines is affected. A logic I is written into all the memory cells in the memory structure. An opposite voltage polarity is caused on the bitlines due to the logic 1 in the memory cells. A reverse voltage polarity stress is achieved on the wordlines by flipping the state of the lowest predecoded line (i.e., by changing the input address corresponding to that line.

Abstract translation: 本发明涉及并行地应用分层存储器结构的系统和方法，测试弱缺陷的存储器结构。 本发明包括将逻辑0写入到存储器结构中的所有存储单元中。 所有高地址预编码线路和最低地址的交替预编码线路都被使能。 相邻字线和位线之间的电压降受到影响。 逻辑I被写入存储器结构中的所有存储器单元。 由于存储器单元中的逻辑1，在位线上产生相反的电压极性。 通过翻转最低预编码行的状态（即，通过改变对应于该行的输入地址），在字线上实现反向电压极性应力。

公开(公告)号：US20080137391A1

公开(公告)日：2008-06-12

申请号：US12018996

申请日：2008-01-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C5/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column.

Abstract translation: 在一个实施例中，提供了动态随机存取存储器（DRAM），其包括：布置成行和列的多个存储单元，其中每个存储单元包括耦合到存储晶体管的存取晶体管，每个存取晶体管布置成矩形 具有长度大于宽度的长度，长度与相应的列对齐，所述存取晶体管耦合到具有大于矩形形状的宽度的宽度的存储晶体管，所述存取晶体管的长度与对应的行对齐， 每个存储单元是L形的，并且其中每列中的L形存储单元相对于相邻列交错排列，使得给定列中的L形存储单元与L形存储单元互锁 相邻列。

公开(公告)号：US20080137390A1

公开(公告)日：2008-06-12

申请号：US12018860

申请日：2008-01-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C5/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of the columns is crossed by a bit line; a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer coupling its corresponding sense amplifier to its corresponding four bit lines.

Abstract translation: 在一个实施例中，提供了动态随机存取存储器（DRAM），其包括：多行存储器单元，每个存储单元行被排列成列，其中每个存储单元行被四行 字线，并且其中每个列被位线交叉; 对应于位线的多个读出放大器，使得单个读出放大器对应于每四位位线; 以及对应于多个读出放大器的多个4：1复用器，每个4：1多路复用器将其对应的读出放大器耦合到其对应的四位线。

公开(公告)号：US20080083942A1

公开(公告)日：2008-04-10

申请号：US11536524

申请日：2006-09-28

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: H01L29/788 ,  G11C11/24

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C2216/10 ,  H01L27/115

Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.

Abstract translation: 非易失性存储单元包括浮置栅极晶体管，其具有耦合到在一个或多个金属层中限定的金属层电容器的浮置栅极。 在每个金属层内，金属层电容器包括耦合到浮动栅极的第一板和通过边缘电容结与第一板隔开的第二板。

公开(公告)号：US20080074915A1

公开(公告)日：2008-03-27

申请号：US11747390

申请日：2007-05-11

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C17/00 ,  G11C17/16

CPC classification number: G11C17/16

Abstract: A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary antifuses is stressed by a programming voltage. The programming voltage stress one a particular one of the complementary antifuses indicates a logical state of the memory cell. For example, a logical high state may correspond to a first one of the complementary antifuses being stressed whereas a logical low state may correspond to the stressing of the remaining one of the complementary antifuses.

Abstract translation: 一次性可编程存储器单元使用以互补方式编程的两个互补反熔丝，使得仅两个互补反熔丝中的仅一个被编程电压施加。 补充反熔丝中的特定一个的编程电压应力指示存储器单元的逻辑状态。 例如，逻辑高状态可以对应于被应力的互补反熔丝中的第一个，而逻辑低状态可以对应于剩余的一个互补反熔丝的应力。

公开(公告)号：US20070297266A1

公开(公告)日：2007-12-27

申请号：US11766200

申请日：2007-06-21

Applicant: Ali Anvar ,  Gil Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil Winograd ,  Esin Terzioglu

IPC: G11C8/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。

公开(公告)号：US07260020B2

公开(公告)日：2007-08-21

申请号：US11191803

申请日：2005-07-28

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G11C8/18

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。