公开(公告)号：US20120066571A1

公开(公告)日：2012-03-15

申请号：US13220453

申请日：2011-08-29

Applicant: Fabrice Marinet

Inventor： Fabrice Marinet

IPC: G06F11/16

CPC classification number: H04L9/0866 ,  G06F21/73 ,  G11C7/1006 ,  G11C7/20 ,  G11C7/24 ,  G11C11/41 ,  G11C29/52 ,  G11C2029/0407 ,  H04L2209/04 ,  H04L2209/34

Abstract: A method of extraction of a key from a physical unclonable function exploiting the states of cells of a volatile memory after a powering on, wherein: cells are read according to addresses stored in a non-volatile memory; an error-correction code corrects the read states; and, in case an error has been corrected, the address of the cell providing an erroneous state is replaced in the non-volatile memory with that of another cell providing the non-erroneous state.

Abstract translation: 一种从上电开始时利用易失性存储器的单元状态的物理不可克隆功能提取密钥的方法，其中：根据存储在非易失性存储器中的地址读取单元; 纠错码纠正读取状态; 并且在错误已被纠正的情况下，提供错误状态的单元的地址在非易失性存储器中被替换为提供非错误状态的另一个单元的地址。

公开(公告)号：US20110234307A1

公开(公告)日：2011-09-29

申请号：US13071325

申请日：2011-03-24

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G05F3/02 ,  G01R19/00

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The disclosure relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Abstract translation: 本发明涉及一种用于检测电子微电路中的攻击的方法，包括：在衬底中形成所述微电路，在所述衬底中形成第一阱，所述第一阱与所述衬底电隔离，由第二阱和嵌入阱形成， 和第二阱，数据处理电路包括形成在第一阱中的接地端子和形成在第二阱中的电源端子，并且当数据处理电路的接地或电源端子处的电压超过阈值时启动检测信号 电压。

公开(公告)号：US20110113256A1

公开(公告)日：2011-05-12

申请号：US12942557

申请日：2010-11-09

Applicant: Fabrice Marinet ,  Mathieu Lisart

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G06F12/14 ,  G06F12/00

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.

Abstract translation: 该组件包括第一存储器（MM），其包括具有由第一修改实体（K1）修改的内容的第一部分（P1）和具有用第二实体（K2）修改的内容的第二部分（P2），存储装置 （MS）被配置为秘密地存储第一实体（K1），非易失性存储器（NVM）将代表第二实体（K2）的实体信息项存储在由第一指示（INDK2）指定的位置（END）中， 包含在第一存储器的所述第一部分中。

公开(公告)号：US20110080190A1

公开(公告)日：2011-04-07

申请号：US12897217

申请日：2010-10-04

Applicant: Pascal Fornara ,  Fabrice Marinet

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H03K19/00

CPC classification number: H01L23/573 ,  H01L21/26506 ,  H01L21/3223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 μm from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate.

Abstract translation: 一种用于对激光攻击进行保护的方法，在半导体衬底内部和之上形成集成电路芯片，并且在衬底的上部包括形成有部件的有源部分，该方法包括以下步骤： 衬底在有源部分下方延伸的吸气区域，该区域的上限距离衬底的上表面在5至50μm的深度范围内; 并将扩散金属杂质引入衬底中。

公开(公告)号：US20110079881A1

公开(公告)日：2011-04-07

申请号：US12897231

申请日：2010-10-04

Applicant: Pascal Fornara ,  Fabrice Marinet

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L29/32

CPC classification number: H01L23/573 ,  H01L21/26506 ,  H01L21/3221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 μm from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.

Abstract translation: 一种集成电路芯片，形成在半导体衬底的内部和顶部，并且包括：在衬底的上部，形成有部件的有源部分; 并且在活性部分和距离衬底的上表面5至50μm之间的深度范围内，包括用于吸收金属杂质并且含有浓度范围为1017至1018原子/ cm3之间的金属原子的位置的区域。

公开(公告)号：US07871832B2

公开(公告)日：2011-01-18

申请号：US11663219

申请日：2005-09-23

Applicant: Fabrice Marinet

Inventor： Fabrice Marinet

IPC: H01L21/66

CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract translation: 产生支持至少一个集成电路的芯片标识符，其包括通过切割芯片提供至少一个导电路径的切口，切割线相对于芯片的位置调节该标识符。

公开(公告)号：US20080243973A1

公开(公告)日：2008-10-02

申请号：US11663571

申请日：2005-09-27

Applicant: Luc Wuidart ,  Fabrice Marinet

Inventor： Luc Wuidart ,  Fabrice Marinet

IPC: G06F13/00

CPC classification number: G06K19/07372 ,  G06F21/75 ,  G06K19/073 ,  G06K19/07363 ,  G06K19/07716 ,  G06Q20/3558 ,  G07F7/1008 ,  H01L27/0203

Abstract: A method for protecting an integrated circuit. According to the method, the start-up of all, or part, of the circuit is determined in the presence of a key which is recorded in a non-volatile manner in the circuit, following the production thereof, and depends on at least one first parameter which is present in a non-volatile manner in the circuit after the production thereof.

Abstract translation: 一种用于保护集成电路的方法。 根据该方法，电路的全部或部分的启动是在存在按照非易失性方式记录在电路中的密钥之后确定的，并且依赖于至少一个 第一参数在其生产之后在电路中以非易失性方式存在。

公开(公告)号：US20080023854A1

公开(公告)日：2008-01-31

申请号：US11663219

申请日：2005-09-23

Applicant: Fabrice Marinet

Inventor： Fabrice Marinet

IPC: H01L23/544 ,  H01L21/4763

CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract translation: 产生支持至少一个集成电路的芯片标识符，其包括通过切割芯片提供至少一个导电路径的切口，切割线相对于芯片的位置调节该标识符。

公开(公告)号：US07146509B2

公开(公告)日：2006-12-05

申请号：US10004527

申请日：2001-11-01

Applicant: Fabrice Marinet ,  Sylvie Wuidart

Inventor： Fabrice Marinet ,  Sylvie Wuidart

IPC: G06F12/14

CPC classification number: G06F21/755 ,  G06F2221/2143

Abstract: Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.

公开(公告)号：US20060124928A1

公开(公告)日：2006-06-15

申请号：US11302620

申请日：2005-12-14

Applicant: Fabrice Marinet

Inventor： Fabrice Marinet

IPC: H01L23/58

CPC classification number: H01L27/0203 ,  G01R31/01 ,  G01R31/31719 ,  G11C7/24 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and a circuit for protecting at least one element of an integrated circuit, including conditioning the operation of the element to be protected to the state of a signal conditioned by an irreversibly programmable element, the state of which is set during a probe test of the integrated circuit.

Abstract translation: 一种用于保护集成电路的至少一个元件的方法和电路，包括调整要被保护的元件的操作到由不可逆可编程元件调节的信号的状态，其状态是在探针测试期间设置的 集成电路。