公开(公告)号：US20200219813A1

公开(公告)日：2020-07-09

申请号：US16240335

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Lars W. Liebmann ,  Ruilong Xie

IPC: H01L23/535 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/306 ,  H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

公开(公告)号：US20200185374A1

公开(公告)日：2020-06-11

申请号：US16214450

申请日：2018-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joseph Versaggi

IPC: H01L27/02 ,  H01L27/105 ,  G11C5/06 ,  H01L21/768 ,  H01L43/12 ,  H01L45/00

Abstract: Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

公开(公告)号：US10665281B1

公开(公告)日：2020-05-26

申请号：US16286942

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L27/22

Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.

公开(公告)号：US10418449B2

公开(公告)日：2019-09-17

申请号：US15866855

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L21/70 ,  H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

公开(公告)号：US10236215B1

公开(公告)日：2019-03-19

申请号：US15791711

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

公开(公告)号：US10056377B2

公开(公告)日：2018-08-21

申请号：US15786164

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Bipul C. Paul

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L29/78

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

公开(公告)号：US20140299941A1

公开(公告)日：2014-10-09

申请号：US13856548

申请日：2013-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/412

Abstract: A mesh circuit for the VSS supply voltage of a SRAM device is disclosed. Embodiments also provide a SRAM bitcell design comprising a VSS mesh disposed in two different metal layers. One metal layer includes horizontal VSS lines, while another metal layer includes vertical VSS lines. A via layer disposed between the first metal layer and second metal layer connects the two metal layers together.

Abstract translation: 公开了一种用于SRAM器件的VSS电源电压的栅极电路。 实施例还提供了一种SRAM位单元设计，其包括设置在两个不同金属层中的VSS网格。 一个金属层包括水平的VSS线，而另一个金属层包括垂直的VSS线。 布置在第一金属层和第二金属层之间的通孔层将两个金属层连接在一起。

公开(公告)号：US10811069B2

公开(公告)日：2020-10-20

申请号：US16248279

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Harsh N. Patel ,  Bipul C. Paul

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L29/423 ,  H01L21/8238 ,  H01L43/02 ,  H01F10/32

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.

公开(公告)号：US10720391B1

公开(公告)日：2020-07-21

申请号：US16240335

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Lars W. Liebmann ,  Ruilong Xie

IPC: H01L23/00 ,  H01L23/535 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L27/11 ,  H01L21/02 ,  H01L29/66

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

公开(公告)号：US10707218B2

公开(公告)日：2020-07-07

申请号：US16045920

申请日：2018-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie

IPC: H01L27/11 ,  H01L27/12 ,  G11C11/412 ,  H01L29/06

Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.