公开(公告)号：US20170018463A1

公开(公告)日：2017-01-19

申请号：US14800970

申请日：2015-07-16

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract translation: 晶体管器件包括衬底; 形成在所述基板上的源极区域和漏极区域; 以及与所述源极区域和所述漏极区域中的至少一个接触形成的源极/漏极接触部，所述源极/漏极接触部包括导电金属和设置在所述导电金属与所述源极和漏极区域中的至少一个之间的双层 包括与导电金属接触的金属氧化物层的双层以及与源区和漏区中的至少一个接触的二氧化硅层。

公开(公告)号：US09397003B1

公开(公告)日：2016-07-19

申请号：US14722818

申请日：2015-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76801 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: A method includes forming a first confined raised source/drain region between an adjacent pair of first dummy gate structures and a second confined raised source/drain region between an adjacent pair of second dummy gate structures during a same first epitaxial growth process, the first and second confined raised source/drain regions including a first semiconductor material. Thereafter, a replacement metal gate process is performed to replace the pairs of first and second dummy gate structures with respective pairs of first and second replacement gate structures. After the replacement metal gate process is performed, a first contact element is formed to the first confined raised source/drain region, a second epitaxial growth process is performed to form a layer of a second semiconductor material above the second confined raised source/drain region, and a second contact element is formed to the layer of second semiconductor material layer.

Abstract translation: 一种方法包括在相同的第一外延生长过程期间在相邻的第一伪栅极结构对之间形成第一限制的凸起源极/漏极区域和在相邻的第二虚拟栅极结构对之间的第二限定的凸起的源极/漏极区域，第一和第 包括第一半导体材料的第二受限升高的源极/漏极区域。 此后，执行替换金属栅极处理以用相应的第一和第二替代栅极结构对来替换第一和第二伪栅极结构对。 在执行替换金属栅极处理之后，对第一限制凸起源极/漏极区域形成第一接触元件，执行第二外延生长工艺以在第二限制的凸起源极/漏极区域上方形成第二半导体材料层 并且第二接触元件形成到第二半导体材料层的层。

公开(公告)号：US10833019B2

公开(公告)日：2020-11-10

申请号：US16668409

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L23/485 ,  H01L21/285 ,  H01L29/66

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US20190157413A1

公开(公告)日：2019-05-23

申请号：US16237685

申请日：2019-01-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/285 ,  H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/161 ,  H01L23/485

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US10236218B1

公开(公告)日：2019-03-19

申请号：US15900264

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Hiroaki Niimi ,  Nigel Cave ,  Xusheng Kevin Wu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213

Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising dual silicides in contacts to FinFETs. The semiconductor device may comprise a PFET fin; an NFET fin; a first metal silicide around the NFET fin; a second metal silicide around the PFET fin; and a fill metal around the second metal silicide, above the PFET fin, and above the NFET fin. Methods of forming such devices are also disclosed.

公开(公告)号：US09853115B2

公开(公告)日：2017-12-26

申请号：US15272919

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/768 ,  H01L29/45 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285 ,  H01L27/092 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US20160351566A1

公开(公告)日：2016-12-01

申请号：US15175540

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Ruilong Xie

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76801 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. An etch stop layer is positioned above and covers a portion of the active region, an interlayer dielectric material is positioned above the active region and covers the etch stop layer, and a confined raised source/drain region is positioned on and in contact with an upper surface of the active region. The confined raised source/drain region extends laterally between and contacts a lower sidewall surface portion of the sidewall spacer and at least a portion of a sidewall surface of the etch stop layer, and a conductive contact element extends through the interlayer dielectric material and directly contacts an upper surface of the confined raised source/drain region.

Abstract translation: 半导体器件包括横向限定半导体衬底中的有源区的隔离区，位于有源区上方的栅极结构和邻近栅结构的侧壁定位的侧壁间隔。 蚀刻停止层位于有源区的上方并覆盖其一部分，层间电介质材料位于有源区上方并覆盖蚀刻停止层，并且限定的凸起源极/漏极区位于上部 活性区域的表面。 限制的升高的源极/漏极区域横向延伸并且接触侧壁间隔件的下侧壁表面部分和蚀刻停止层的侧壁表面的至少一部分，并且导电接触元件延伸穿过层间绝缘材料并直接接触 受限升高的源极/漏极区域的上表面。

公开(公告)号：US09484255B1

公开(公告)日：2016-11-01

申请号：US14930933

申请日：2015-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

Abstract translation: 一种电气装置，包括具有硅和锗的源极和漏极区域的第一半导体器件，以及具有含硅源极和漏极区域的第二半导体器件。 与所述第一半导体器件的所述含硅和含锗的源极和漏极区域中的至少一个接触的第一器件包括铝钛和硅合金的金属衬垫和第一钨填充物。 第二器件触点与第二半导体器件的含硅源极和漏极区域中的至少一个接触，包括氧化钛层和钛层的材料堆叠。 第二器件接触件还可以包括第二钨填充物。

公开(公告)号：US10475904B2

公开(公告)日：2019-11-12

申请号：US15868004

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Steven Bentley ,  Romain Lallement ,  Brent A. Anderson ,  Junli Wang ,  Muthumanickam Sankarapandian

IPC: H01L29/66 ,  H01L29/778 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/11 ,  H01L21/8238

Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

公开(公告)号：US20190214484A1

公开(公告)日：2019-07-11

申请号：US15868004

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Steven Bentley ,  Romain Lallement ,  Brent A. Anderson ,  Junli Wang ,  Muthumanickam Sankarapandian

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/092

Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.