公开(公告)号：US09716136B1

公开(公告)日：2017-07-25

申请号：US15071641

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/525 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: A method of forming an embedded polysilicon resistor body contact. According to the method, a transistor is formed in and above a crystalline active region that is positioned in a semiconductor layer of a multilayer semiconductor device. A resistor region is defined in single crystal semiconductor material of the semiconductor layer formed on a buried insulating layer. The resistor region is adjacent the transistor. An amorphized semiconductor material is formed in the resistor region. A barrier is formed in the amorphized semiconductor material. The barrier is between the transistor and an electrical body contact for the transistor. The amorphized semiconductor material is annealed, forming a polysilicon semiconductor. The barrier prevents the amorphized region from recrystallizing back to single crystal silicon.

公开(公告)号：US20160170140A1

公开(公告)日：2016-06-16

申请号：US15041103

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/132 ,  G02B6/122 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

公开(公告)号：US20210066118A1

公开(公告)日：2021-03-04

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/265 ,  H01L29/06

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

公开(公告)号：US10466514B1

公开(公告)日：2019-11-05

申请号：US16181879

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02F1/035 ,  G02F1/225 ,  G02B6/122 ,  G02B6/136 ,  F21V8/00 ,  G02F1/015 ,  G02F1/21 ,  G02B6/12

Abstract: Structures for an electro-optic modulator and methods of fabricating such structures. A first plurality of cavities are formed in a bulk semiconductor substrate. A passive waveguide arm includes a first core arranged over the first plurality of cavities. The passive waveguide arm has an input port and an output port that is spaced lengthwise from the input port. An epitaxial semiconductor layer is arranged over the bulk semiconductor substrate, and includes a second plurality of cavities. An active waveguide arm includes a second core that is arranged over the second plurality of cavities. The second core of the active waveguide arm is coupled with the input port of the first core of the passive waveguide arm, and the second core of the active waveguide arm is also coupled with the output port of the first core of the passive waveguide arm.

公开(公告)号：US20190295881A1

公开(公告)日：2019-09-26

申请号：US16218868

申请日：2018-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US20190265406A1

公开(公告)日：2019-08-29

申请号：US15905165

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136

Abstract: Waveguide structures and methods of fabricating waveguide structures. A first airgap is formed in a bulk semiconductor substrate, and a semiconductor layer is epitaxially grown over the bulk semiconductor substrate and the first airgap. First and second trench isolation regions extend through the semiconductor layer and into the bulk semiconductor substrate, and are spaced to define a waveguide core region including a section of the bulk semiconductor substrate and a section of the semiconductor layer that are arranged between the first and second trench isolation regions. A dielectric layer is formed over the waveguide core region, and a second airgap is formed in the dielectric layer. The first airgap is arranged in the bulk semiconductor substrate between the first trench isolation region and the second trench isolation region and under the waveguide core region. The second airgap in the dielectric layer is arranged over the waveguide core region.

公开(公告)号：US20190229184A1

公开(公告)日：2019-07-25

申请号：US15876530

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Cameron Luce ,  Pernell Dongmo

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78

Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

公开(公告)号：US10263013B2

公开(公告)日：2019-04-16

申请号：US15441711

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/84 ,  H01L49/02 ,  H01L21/265 ,  H01L29/08 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US10224396B1

公开(公告)日：2019-03-05

申请号：US15817629

申请日：2017-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Daisy Vaughn ,  Thai Doan

IPC: H01L29/00 ,  H01L29/06 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to deep trench isolation structures and methods of manufacture. The structure includes: at least one gate structure on a substrate; an interlevel dielectric material above the substrate; and a trench isolation structure extending into the substrate adjacent to the at least one gate structure and terminating in the interlevel dielectric material above the substrate.

公开(公告)号：US10192779B1

公开(公告)日：2019-01-29

申请号：US15935606

申请日：2018-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.