公开(公告)号：US09639650B2

公开(公告)日：2017-05-02

申请号：US14716565

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim

IPC: G06F17/50 ,  H01L21/00 ,  H01L21/027

CPC classification number: H01L23/5286 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/027 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L28/00 ,  Y02P90/265

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.

公开(公告)号：US09634003B2

公开(公告)日：2017-04-25

申请号：US15063563

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US09530780B2

公开(公告)日：2016-12-27

申请号：US15140548

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

Abstract translation: 公开了一种用于提供具有小型化位单元的SRAM位单元的方法，没有本地互连层，具有改进的平版印刷可印刷性和使能方法。 实施例包括在M1层中提供包括第一字线，第一位线，第二位线，第一接地线，第二接地线，第二锁存线或其组合的第一颜色结构，其中第一 颜色结构包括比边缘长的侧边缘; 在M1层中提供第二颜色结构，包括第二字线，第一电源线，第二电源线，第一锁存线或其组合，其中第二颜色结构包括比尖端边缘长的侧边缘; 以及形成包括所述第一颜色结构和所述第二颜色结构的位单元，其中相邻的尖端边缘包括第一颜色结构的尖端边缘和第二颜色结构的尖端边缘。

公开(公告)号：US09391080B1

公开(公告)日：2016-07-12

申请号：US14698066

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

公开(公告)号：US09337099B1

公开(公告)日：2016-05-10

申请号：US14610260

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L21/44 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract translation: 提供了用于使具有不同大小的扩散区域的两个电池邻接的方法以及所得到的装置。 实施例包括：通过在两个单元之间的边界处形成虚拟栅极来邻接具有第一漏极和源极扩散区域的第一单元和具有大于第一扩散区域的第二漏极和源极扩散区域的第二单元; 形成连续的漏极扩散区域，其具有与伪栅极交叉的上部，并且包围整个第一漏极扩散区域和第二漏极扩散区域的一部分，并且具有从伪栅极开始的下部，并且包围第二漏极扩散区域的剩余部分 ; 形成作为连续漏极扩散区域的镜像的连续源极扩散区域; 以及在连续的漏极和源极扩散区之间在虚拟栅极之间形成多边形掩模，但是与连续的漏极和源极扩散区分离。

公开(公告)号：US20150331988A1

公开(公告)日：2015-11-19

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US09122830B2

公开(公告)日：2015-09-01

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US08962483B2

公开(公告)日：2015-02-24

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/3065 ,  H01L21/308 ,  G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。

公开(公告)号：US08916441B2

公开(公告)日：2014-12-23

申请号：US13893684

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye ,  Suresh Venkatesan

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681

Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.

Abstract translation: 本发明的实施例提供了用于形成包含标准单元的finFET结构的新颖方法和结构。 使用H形切割掩模来减少需要去除的翅片的数量，从而提高翅片效率。

公开(公告)号：US20140353842A1

公开(公告)日：2014-12-04

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处连接到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。