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    Methods of forming replacement fins for a FinFET device
    31.
    发明授权
    Methods of forming replacement fins for a FinFET device 有权
    形成FinFET器件的替代鳍片的方法

    公开(公告)号：US09324618B1

    公开(公告)日：2016-04-26

    申请号：US14727364

    申请日：2015-06-01

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

    IPC: H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8234

    CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

    Abstract: One illustrative method includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a substrate fin, forming a layer of insulating material in the trenches, and forming a layer of CTE-matching material above the upper surface of the layer of insulating material, wherein the layer of CTE-matching material has a CTE that is within ±20% of the replacement fin CTE and wherein the layer of CTE-matching material partially defines a replacement fin cavity that exposes an upper portion of the substrate fin. In this example, the method also includes forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

    Abstract translation: 一种说明性方法包括在半导体衬底中形成多个沟槽，以便限定衬底鳍，在沟槽中形成绝缘材料层，并在上表面上方形成一层CTE匹配材料 所述绝缘材料层，其中所述CTE匹配材料层具有在替换翅片CTE的±20％内的CTE，并且其中所述CTE匹配材料层部分地限定了将所述CTE匹配材料的上部 底片 在该示例中，该方法还包括在基板翅片和替换翅片腔上形成替换翅片，去除CTE匹配材料层并在替换翅片的至少一部分周围形成栅极结构。

    Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials
    33.
    发明授权
    Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials 有权
    为具有替代通道材料的FinFET半导体器件形成隔离鳍片的方法

    公开(公告)号：US09147616B1

    公开(公告)日：2015-09-29

    申请号：US14471087

    申请日：2014-08-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

    IPC: H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795

    Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

    Abstract translation: 本文公开的一种说明性方法包括氧化初始鳍结构的下部，从而限定将初始鳍结构的上部与半导体衬底垂直分离的隔离区，执行凹陷蚀刻工艺以去除 初始翅片结构的上部的一部分，以便限定一个凹入的翅片部分，在该凹入的翅片部分上形成一个替换翅片，以便限定由替换翅片和该凹入的翅片部分组成的最终翅片结构， 围绕替换翅片的至少一部分的门结构。

    Fin pitch scaling and active layer isolation
    34.
    发明授权
    Fin pitch scaling and active layer isolation 有权
    鳍间距缩放和有源层隔离

    公开(公告)号：US09076842B2

    公开(公告)日：2015-07-07

    申请号：US14011125

    申请日：2013-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven John Bentley ,  Bartlomiej Jan Pawlak

    IPC: H01L21/302 ,  H01L21/764 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

    Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

    Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs
    36.
    发明授权
    Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs 有权
    栅极长度独立无硅（SON）方案用于散装FinFET

    公开(公告)号：US09006077B2

    公开(公告)日：2015-04-14

    申请号：US13971937

    申请日：2013-08-21

    Applicant: GlobalFoundries, Inc.

    Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

    IPC: H01L21/76 ,  H01L21/84 ,  H01L21/00 ,  H01L21/762 ,  H01L21/02

    CPC classification number: H01L21/76264 ,  H01L21/02488 ,  H01L21/76224 ,  H01L29/66795

    Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

    Abstract translation: 提供了在具有与绝缘体与衬底隔离的有源沟道区的本体衬底上制造集成电路和FinFET晶体管的方法。 根据示例性实施例，一种用于制造集成电路的方法包括形成覆盖半导体衬底的鳍状结构，其中每个鳍结构包括沟道材料并且在纵向方向上从第一端延伸到第二端。 该方法将锚固材料沉积在翅片结构上。 该方法包括使锚固材料凹入以形成邻近翅片结构的沟槽，其中锚定材料保持与每个翅片结构的第一端和第二端接触。 此外，该方法在半导体衬底和每个鳍结构的沟道材料之间形成空隙，栅极长度独立蚀刻工艺，其中每个鳍结构的沟道材料悬置在半导体衬底上。

    METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING
    38.
    发明申请
    METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING 审中-公开
    通过现场掺杂分离Si的器件分离方法

    公开(公告)号：US20140374807A1

    公开(公告)日：2014-12-25

    申请号：US13921265

    申请日：2013-06-19

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce B. Doris ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/785 ,  H01L29/66803

    Abstract: Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation.

    Abstract translation: 本发明的方面涉及一种用于形成在硅衬底上具有一组散热片的集成电路的方法，该散热片组根据预定图案形成。 在沉积外延层之前用N型掺杂剂原位掺杂散热片使冲击穿孔最小化，而外延沉积工艺在掺杂的翅片上施加覆层，沉积导致具有改进的器件隔离的多器件装置。

    Electrically insulated fin structure(s) with alternative channel materials and fabrication methods
    39.
    发明授权
    Electrically insulated fin structure(s) with alternative channel materials and fabrication methods 有权

    公开(公告)号：US10163677B2

    公开(公告)日：2018-12-25

    申请号：US15848371

    申请日：2017-12-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

    IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

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