公开(公告)号：US20060002173A1

公开(公告)日：2006-01-05

申请号：US10882860

申请日：2004-06-30

申请人： Ward Parkinson ,  Charles Dennison ,  Stephen Hudgens

发明人： Ward Parkinson ,  Charles Dennison ,  Stephen Hudgens

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/76

摘要： A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

摘要翻译： 存储器可以包括相变存储器元件和串联连接的第一和第二选择器件。 第二选择装置可以具有比第一选择装置更高的电阻和更大的阈值电压。 在一个实施例中，第一选择装置可以具有基本上等于其保持电压的阈值电压。 在一些实施例中，选择装置和存储元件可以由硫族化物制成。 在一些实施例中，选择装置可以由不可编程的硫族化物制成。 具有较高阈值电压的选择装置可能会对组合造成较低的泄漏，但也可能表现出增加的快速恢复。 这种增加的快速恢复可以被具有较低阈值电压的选择装置抵消，导致在一些实施例中与低泄漏和高性能的组合。

公开(公告)号：US06781860B2

公开(公告)日：2004-08-24

申请号：US10137476

申请日：2002-05-01

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C1700

CPC分类号： G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  G11C16/02 ,  G11C16/10

摘要： A driver circuit having one or more MOS transistors. The driver circuit is capable of providing an output voltage greater than the power supply voltage; however, the magnitude of the voltages appearing across the terminals of the MOS transistors are preferably less than or equal to the magnitude of the power supply voltage. The driver circuit may comprise a plurality of serially coupled PMOS transistors and a plurality of serially coupled NMOS transistors wherein the plurality of PMOS transistors and plurality of NMOS transistors are coupled at the output node of the driver.

摘要翻译： 一种具有一个或多个MOS晶体管的驱动电路。 驱动电路能够提供大于电源电压的输出电压; 然而，MOS晶体管的端子两端出现的电压的大小优选小于或等于电源电压的大小。 驱动器电路可以包括多个串联耦合的PMOS晶体管和多个串联耦合的NMOS晶体管，其中多个PMOS晶体管和多个NMOS晶体管耦合在驱动器的输出节点处。

公开(公告)号：US5831927A

公开(公告)日：1998-11-03

申请号：US848340

申请日：1997-04-30

申请人： Stephen L. Casper ,  Ward Parkinson

发明人： Stephen L. Casper ,  Ward Parkinson

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1015 ,  G11C8/18

摘要： A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition. Alternatively, the memory device may include a row decoder that is coupled between the latch and the array, and enables a row of memory cells identified by the row address. A control circuit is coupled to the array, receives the row address strobe, and enables the array to output additional data from the identified row even when the row address strobe is at the inactive level. Furthermore, the memory device may include both the control circuit and the row decoder that allows the row address to propagate therethrough while the row address strobe is at an inactive level.

公开(公告)号：US20160064076A1

公开(公告)日：2016-03-03

申请号：US14791463

申请日：2015-07-05

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C13/00

CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76

摘要： A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

公开(公告)号：US09076521B2

公开(公告)日：2015-07-07

申请号：US13549436

申请日：2012-07-14

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76

摘要： A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

公开(公告)号：US08767440B2

公开(公告)日：2014-07-01

申请号：US13892499

申请日：2013-05-13

申请人： Ward Parkinson ,  Thomas Trent

发明人： Ward Parkinson ,  Thomas Trent

IPC分类号： G11C11/00

CPC分类号： G11C13/0033 ,  G11C11/22 ,  G11C13/0023

摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

摘要翻译： 一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。 该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。 相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。 此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。 该方案的优点包括防止短路引起阵列过剩的电流，并将由短路引起的读或写故障的频率限制在可管理的数量上。 在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。 示例性实施例包括相变存储器阵列。

公开(公告)号：US08503219B2

公开(公告)日：2013-08-06

申请号：US13158531

申请日：2011-06-13

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.

摘要翻译： 可编程电阻存储器采用反馈控制电路来调节提供给选定的可编程电阻存储元件的编程电流。 可编程电阻存储器可以是相变存储器。 反馈控制电路监视和控制用于编程存储器单元的电流脉冲的特性。

公开(公告)号：US20120281492A1

公开(公告)日：2012-11-08

申请号：US13549437

申请日：2012-07-14

申请人： Ward Parkinson

发明人： Ward Parkinson

IPC分类号： G11C8/10

CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76

摘要： A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller.

公开(公告)号：US20120069622A1

公开(公告)日：2012-03-22

申请号：US12884413

申请日：2010-09-17

申请人： Ward Parkinson ,  Thomas Trent

发明人： Ward Parkinson ,  Thomas Trent

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C11/00

CPC分类号： G11C13/0033 ,  G11C11/22 ,  G11C13/0023

摘要： An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

摘要翻译： 一种具有管理误差校正需求的短路缺陷的非易失性存储器阵列的寻址方案。 该方案通常避免在写入期间同时主动驱动所选单元的行线和列线。 相反，只有单行或列行在任何一个时间被主动驱动，所有其他的数组行都是浮动的。 此外，可以限制在取出期间从给定的行或列访问的存储器单元的数量。 该方案的好处包括防止短路引起阵列过剩的电流，并将由短路导致的读或写故障的频率限制在可管理的数量上。 在一个实施例中，该方案将对错误校正的需求保持在闪存控制器的纠错能力内。 示例性实施例包括相变存储器阵列。

公开(公告)号：US07808807B2

公开(公告)日：2010-10-05

申请号：US12075665

申请日：2008-03-13

申请人： Ward Parkinson ,  Stefan Lai

发明人： Ward Parkinson ,  Stefan Lai

IPC分类号： G11C5/06

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5641

摘要： A memory is configurable among a plurality of operational modes and types of interfaces. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix. Individual operational modes may be matched to individual interfaces, operated one at a time or in parallel.

摘要翻译： 存储器可在多种操作模式和类型的接口之间配置。 操作模式可以指定与存储器存储矩阵内的每个单元相关联的存储级别的数量。 各个操作模式可以与单个接口匹配，每次操作一个或一个并行操作。