公开(公告)号：US20090218629A1

公开(公告)日：2009-09-03

申请号：US12260147

申请日：2008-10-29

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Peter Huebler ,  Kerstin Ruttloff

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Peter Huebler ,  Kerstin Ruttloff

IPC分类号： H01L47/00 ,  H01L21/31

CPC分类号： H01L21/76826 ,  H01L21/76832 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843 ,  Y02P80/30

摘要： In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.

摘要翻译： 在双重应力衬垫方法中，可以基于等离子体辅助氧化工艺而不是通过沉积来提供中间蚀刻停止材料，从而减小蚀刻停止材料的对应厚度。 因此，与常规策略相比，所产生的纵横比可能不太明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件。

公开(公告)号：US07419867B2

公开(公告)日：2008-09-02

申请号：US11154878

申请日：2005-06-16

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

IPC分类号： H01L21/8238

CPC分类号： H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.

摘要翻译： 通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。 掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。

公开(公告)号：US07067410B2

公开(公告)日：2006-06-27

申请号：US10835182

申请日：2004-04-29

申请人： Karsten Wieczorek ,  Thorsten Kammler ,  Manfred Horstmann

发明人： Karsten Wieczorek ,  Thorsten Kammler ,  Manfred Horstmann

IPC分类号： H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/665

摘要： The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

摘要翻译： 本发明提供了一种用于形成诸如二硅化钴之类的金属硅化物的技术，即使在极度缩放的器件尺寸下，也不会不利地降低金属硅化物的膜完整性。 为此，可以在最终退火循环之前有利地利用硅进行离子注入，从而相应地改变金属硅化物的前体的晶粒结构。

公开(公告)号：US06821887B2

公开(公告)日：2004-11-23

申请号：US10391243

申请日：2003-03-18

申请人： Karsten Wieczorek ,  Stephan Kruegel ,  Manfred Horstmann ,  Thomas Feudel

发明人： Karsten Wieczorek ,  Stephan Kruegel ,  Manfred Horstmann ,  Thomas Feudel

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507

摘要： The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

摘要翻译： MOS晶体管的多晶硅栅电极可以基本上完​​全转变为金属硅化物，而不牺牲漏极和源极结，因为用于形成栅电极的多晶硅层的厚度被靶向为基本上转化为金属硅化物 随后的硅化工艺。 基本上由金属硅化物组成的栅极电极甚至在深亚微米范围内的临界尺寸下也提供高导电性，同时多晶硅栅极耗尽的效果显着降低。 具有基本上完全转换的金属硅化物栅电极的MOS晶体管的制造基本上与标准MOS工艺技术相兼容。

公开(公告)号：US06812074B2

公开(公告)日：2004-11-02

申请号：US10391255

申请日：2003-03-18

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krueger

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krueger

IPC分类号： H01L21339

CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78684 ,  Y10S438/933 ,  Y10S438/938

摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

公开(公告)号：US06358826B1

公开(公告)日：2002-03-19

申请号：US09838389

申请日：2001-04-19

申请人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

发明人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

IPC分类号： H01L2144

CPC分类号： H01L29/7833 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28518 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

摘要： A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

摘要翻译： 提供了一种用于在结构上制造半导体器件的方法，该方法包括形成与该半导体器件的栅极导体相邻并且在该结构的LDD区之上的电介质层，并且形成与介电层的第一部分相邻的第一电介质间隔物 邻近栅极导体并且位于LDD区域上方的电介质层的第二部分之上。 该方法还包括将掺杂剂引入到该结构的源极/漏极区域中，并且去除栅极导体上方的电介质层的第三部分，在LDD区域上方的电介质层的第二部分和第一电介质间隔物。 此外，该方法包括在栅极导体上方形成第一导电层，邻近电介质层的第一部分并且位于LDD区之上，并且在栅极导体上方和LDD区之上对第一导电层进行水蚀以形成第一 导电层。

公开(公告)号：US06352885B1

公开(公告)日：2002-03-05

申请号：US09579310

申请日：2000-05-25

申请人： Karsten Wieczorek ,  Frederick N. Hause ,  Manfred Horstmann

发明人： Karsten Wieczorek ,  Frederick N. Hause ,  Manfred Horstmann

IPC分类号： H01L21336

CPC分类号： H01L29/42368 ,  H01L21/26586 ,  H01L29/6659 ,  Y10S438/981

摘要： A transistor having a gate insulation layer whose peripheral portion has an increased thickness and a method of fabricating these transistor devices is disclosed. The peripheral portions with increased thickness of the gate insulation layer significantly reduce the injection of charge carriers into the gate insulation layer. Accordingly, the transistors described in the present application exhibit an improved long-time reliability. In addition, the lateral penetration of ions beneath the gate insulation layer for forming the lightly-doped drain and/or the lightly doped source is increased since the implantation may be performed at a tilt angle with respect to the perpendicular direction which is the conventionally used direction of the implantation step.

摘要翻译： 公开了具有其周边部分具有增加的厚度的栅极绝缘层的晶体管以及制造这些晶体管器件的方法。 具有增加的栅极绝缘层厚度的周边部分显着地减少了电荷载流子注入到栅极绝缘层中。 因此，本申请中描述的晶体管具有改善的长时间可靠性。 此外，由于可以相对于常规使用的垂直方向以倾斜角度进行注入，因此增加了用于形成轻掺杂漏极和/或轻掺杂源的栅极绝缘层下方的离子的横向穿透 注入步骤的方向。

公开(公告)号：US06344397B1

公开(公告)日：2002-02-05

申请号：US09477960

申请日：2000-01-05

申请人： Manfred Horstmann ,  Karsten Wieczorek ,  Bernd Engelmann

发明人： Manfred Horstmann ,  Karsten Wieczorek ,  Bernd Engelmann

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/7833

摘要： In one illustrative embodiment, the present invention is directed to forming a masking layer (104) above a semiconducting substrate (102), forming an opening (105) in the masking layer (104), forming sidewall spacers (109) that define an exposed surface of said substrate lying between the sidewall spacers (109), and forming a layer of gate dielectric material (108) on the exposed surface of the substrate. The method further comprises forming a layer of polysilicon in the opening (105) and on the gate dielectric layer (108), removing portions of the polysilicon layer lying outside the opening (105) to define a gate electrode (111), forming a layer of refractory metal above the gate electrode (111), converting at least some of the refractory metal layer to a metal silicide region (112) above the gate electrode (111), and removing the masking layer (104).

摘要翻译： 在一个说明性实施例中，本发明涉及在半导体衬底（102）上形成掩模层（104），在掩模层（104）中形成开口（105），形成侧壁间隔物（109），其形成暴露 所述衬底的表面位于侧壁间隔件（109）之间，并且在衬底的暴露表面上形成栅介电材料层（108）。 该方法还包括在开口（105）和栅极电介质层（108）上形成多晶硅层，去除位于开口（105）外部的多晶硅层的部分以限定栅电极（111），形成层 在所述栅电极（111）上方的难熔金属，将所述难熔金属层中的至少一些转化为所述栅电极（111）上方的金属硅化物区域（112），以及去除所述掩模层（104）。

公开(公告)号：US06255703B1

公开(公告)日：2001-07-03

申请号：US09324462

申请日：1999-06-02

申请人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

发明人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

IPC分类号： H01L2976

CPC分类号： H01L29/7833 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28518 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

摘要： A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

摘要翻译： 提供了一种用于在结构上制造半导体器件的方法，该方法包括形成与该半导体器件的栅极导体相邻并且位于该结构的LDD区之上的电介质层，并且形成与该介质层的第一部分相邻的第一电介质间隔物 邻近栅极导体并且位于LDD区域上方的电介质层的第二部分之上。 该方法还包括将掺杂剂引入到该结构的源极/漏极区域中，并且去除栅极导体上方的电介质层的第三部分，在LDD区域上方的电介质层的第二部分和第一电介质间隔物。 此外，该方法包括在栅极导体上方形成第一导电层，邻近电介质层的第一部分并且位于LDD区之上，并且在栅极导体上方和LDD区之上对第一导电层进行水蚀以形成第一 导电层。

公开(公告)号：US06242776B1

公开(公告)日：2001-06-05

申请号：US09324879

申请日：1999-06-02

申请人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

发明人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

IPC分类号： H01L2976

CPC分类号： H01L29/66507 ,  H01L29/665 ,  H01L29/6659

摘要： A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

摘要翻译： 提供了一种用于在结构上制造半导体器件的方法，该方法包括形成与该半导体器件的栅极导体相邻并且位于该结构的LDD区之上的电介质层，并且去除栅极导体上方的电介质层的第一部分，以及 在LDD地区之上。 该方法还包括在栅极导体上方形成第一导电层，邻近电介质层并在LDD区域上方，并将栅极导体上方的第一导电层和LDD区上方的第一导电层浸水以形成浸渍的第一导电层。