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公开(公告)号：US09906468B2
公开(公告)日：2018-02-27
申请号：US13283252
申请日：2011-10-27
IPC分类号： H04L12/933 , H04L12/873
摘要： A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor manages traffic on a per-pipe ID basis to ensure that traffic thresholds are not exceeded.
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公开(公告)号：US08977944B2
公开(公告)日：2015-03-10
申请号：US13325943
申请日：2011-12-14
CPC分类号： G06F11/1004 , G06F11/1016 , G06F11/1076 , H03M13/09
摘要： In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
摘要翻译： 在一个实施例中，系统包括存储器，以及经由地址总线，数据总线和错误代码总线耦合到存储器的存储器控制器。 存储器将数据存储在地址处，并在地址处存储错误代码。 基于相应数据和地址的函数生成错误代码。
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公开(公告)号：US08364851B2
公开(公告)日：2013-01-29
申请号：US10677583
申请日：2003-10-02
IPC分类号： G06F3/00
CPC分类号： G06F15/17381 , G06F12/0817 , G06F2212/621
摘要： A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.
摘要翻译： 公开了一种支持高性能，可扩展和高效的I / O端口协议来连接到I / O设备的系统。 分布式多处理计算机系统包含多个处理器，每个处理器都耦合到实现I / O端口协议的I / O桥ASIC。 一个或多个I / O设备耦合到I / O桥ASIC，每个I / O设备能够通过发送和接收消息分组来访问计算机系统中的机器资源。 计算机系统中的机器资源包括数据块，寄存器和中断队列。 计算机系统中的每个处理器耦合到能够存储处理器之间共享的数据块的存储器模块。 使用基于目录的一致性协议来维护该共享存储器系统中的共享数据块的一致性。 使用与存储系统相同的一致性协议来维护I / O设备读写访问期间传输的数据块的一致性。 只有当I / O桥ASIC具有数据块的排他副本时，I / O桥ASIC才能缓存在I / O设备读或写访问期间传输的数据块。 I / O桥ASIC包括支持数据块的顺序和无序DMA读和写数据流的DMA设备。 由DMA设备执行的数据块的顺序读取流总是导致DMA设备接收不必写入存储器模块的相干数据块。
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公开(公告)号：US07209531B1
公开(公告)日：2007-04-24
申请号：US10397083
申请日：2003-03-26
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , H03K5/133 , H04L7/005 , H04L7/10
摘要： A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.
摘要翻译： 利用粗略延迟调整和精细延迟调整的偏移电路将接收到的数据集中在适当的数据窗口中，并对准数据以进行适当的采样。 在一种方案中，SPI-4协议的训练序列的位状态转换用于调整延迟以对齐转换点。
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公开(公告)号：US07076597B2
公开(公告)日：2006-07-11
申请号：US10685039
申请日：2003-10-14
IPC分类号： G06F12/08
CPC分类号： G06F12/0826
摘要： A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster. All processors within the cluster invalidate a local copy of the shared data if it exists and once the master processor receives acknowledgements from all processors in the cluster, the master processor sends an invalidate acknowledgment message to the processor that originally requested the exclusive rights to the shared data. The cache coherency is scalable and may be implemented using the hybrid point-to-point/broadcast scheme or a conventional point-to-point only directory-based invalidate scheme.
摘要翻译： 用于分发无效消息以改变计算机系统中的共享数据的状态的基于目录的多处理器高速缓存控制方案。 多个处理器被分组成多个簇。 目录控制器跟踪发送到集群中的处理器的共享数据的副本。 当从处理器接收到请求许可修改数据的共享副本的独占请求时，目录控制器产生无效消息，请求共享相同数据的其他处理器使该数据无效。 这些无效消息通过点对点传输仅发送到实际包含数据共享副本的集群中的主处理器。 在收到无效消息后，主处理器将有序扇入/扇出进程中的无效消息广播到群集中的每个处理器。 集群内的所有处理器使共享数据的本地副本（如果存在）无效，并且一旦主处理器从集群中的所有处理器接收到确认，则主处理器向原始请求共享的专有权的处理器发送无效确认消息 数据。 高速缓存一致性是可扩展的，并且可以使用混合点对点/广播方案或常规的仅基于点对点的仅基于目录的无效方案来实现。
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36.发明授权Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing 失效使用同义词/子集处理中的散列来最小化dcache索引匹配混叠的方法和装置公开(公告)号：US06253285B1
公开(公告)日：2001-06-26
申请号：US09116039
申请日：1998-07-15
IPC分类号： C06F1200
CPC分类号： G06F12/1054 , G06F12/0864 , G06F2212/1016 , G06F2212/655
摘要： A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The data store comprises a plurality of data blocks for holding data. The tag array comprises a plurality of tag entries corresponding to the data blocks, and both the data store and tag array are addressed with the cache index. The tag array provides a plurality of physical address tags corresponding to physical addresses of data resident within corresponding data blocks in the data store addressed by the cache index. The page translator translates a tag portion of the virtual address to a corresponding physical address tag. The comparator verifies a match between the physical address tag from the page translator and the plurality of physical address tags from the tag array, a match indicating that data addressed by the virtual address is resident within the data store. Finally, the duplicate tag array resolves synonym issues caused by hashing. The hashing function is such that addresses which are equivalent mod 213 are pseudo-randomly displaced within the cache. The preferred hashing function maps VA to bits of the cache index.
摘要翻译： 数据缓存系统包括散列函数，数据存储器，标签阵列，页面翻译器，比较器和重复的标签阵列。 散列函数将虚拟地址的索引部分与虚拟地址的虚拟页面部分组合以形成高速缓存索引。 数据存储器包括用于保存数据的多个数据块。 标签阵列包括与数据块相对应的多个标签条目，并且数据存储和标签阵列都用高速缓存索引寻址。 标签阵列提供与驻留在由高速缓存索引寻址的数据存储器中的相应数据块内的数据的物理地址相对应的多个物理地址标签。 页面翻译器将虚拟地址的标签部分转换为相应的物理地址标签。 比较器验证来自页面翻译器的物理地址标签与来自标签阵列的多个物理地址标签之间的匹配，指示由虚拟地址寻址的数据驻留在数据存储中的匹配。 最后，重复的标签数组解决哈希引起的同义词问题。 散列函数使得等效的mod 213的地址在高速缓存内被伪随机移位。 优先散列函数将VA <14,15异或13,12：6>映射到高速缓存索引的位<14：6>。
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37.发明授权Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller 失效使用两条数据路径的大规模并行处理系统：一条将路由器电路连接到互连网络，另一条连接路由器电路连接到I / O控制器
公开(公告)号：US5864738A
公开(公告)日：1999-01-26
申请号：US614859
申请日：1996-03-13
IPC分类号： G06F12/08 , G06F15/173 , G06F15/80 , G06G13/00
CPC分类号： G06F15/17375 , G06F12/0817 , G06F15/8007
摘要： A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.
摘要翻译： 在具有互连网络和多个处理节点的外围设备和MPP系统之间传送信息的系统和方法。 每个处理元件包括处理器，本地存储器和连接到互连网络的路由器电路，处理器和本地存储器。 每个路由器电路包括用于在处理器和互连网络之间传送数据的装置和用于在本地存储器和互连网络之间传送数据的装置。 I / O控制器连接到多个路由器电路。 然后从外围设备读取数据，并通过I / O控制器传送到其中一个处理元件的本地存储器。
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38.发明授权
公开(公告)号：US5737628A
公开(公告)日：1998-04-07
申请号：US662868
申请日：1996-06-12
申请人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
发明人： Mark S. Birrittella , Richard E. Kessler , Steven M. Oberlin , Randal S. Passint , Greg Thorson
CPC分类号： H04L45/06 , G06F15/17337 , G06F15/17381 , H04L45/10 , H04L49/101 , H04L49/205 , H04L49/251
摘要： A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
摘要翻译： 用于并行处理计算机的多维互连和路由设备将三维结构中的处理元件连接在一起。 互连和路由设备包括多个处理单元节点。 通信中的至少一个处理元件与主机系统连接。 互连网络将处理元件节点连接在X，Y和Z维度上。 该网络包括将多个处理元件中的每一个连接到X，Y和Z各维度的正负方向的相邻处理元件的通信路径。
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公开(公告)号：US09612934B2
公开(公告)日：2017-04-04
申请号：US13284289
申请日：2011-10-28
CPC分类号： G06F11/3495 , G06F1/3203 , G06F3/16 , G06F11/349 , G06F12/084 , G06F13/385 , G06F13/4022
摘要： A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.
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公开(公告)号：US08885480B2
公开(公告)日：2014-11-11
申请号：US13277613
申请日：2011-10-20
IPC分类号： H04L1/00 , H04L12/931 , H04L12/825
CPC分类号： H04L49/205 , H04L47/263 , H04L49/505
摘要： In a network processor, a “port-kind” identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID is implemented to assign a priority to the packet, as well as determine whether a traffic threshold is exceeded, thereby enabling a backpressure signal to limit packet traffic associated with the particular backpressure ID.
摘要翻译： 在网络处理器中，为每个端口分配“端口类型”标识符（ID）。 解析电路使用端口种类ID来选择与接收到的分组相关联的配置信息。 端口种类ID也可以存储在呈现给软件的数据结构以及更大的端口号（指示接口和/或信道）上。 根据端口种类ID和关于分组的提取信息，计算分组的背压ID。 背压ID被实现以分配分组的优先级，并且确定是否超过流量阈值，从而使背压信号能够限制与特定背压ID相关联的分组流量。
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