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31.发明申请ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效高速总线上的错误纠正代码保护的静态位通信公开(公告)号：US20100005365A1
公开(公告)日：2010-01-07
申请号：US12165788
申请日：2008-07-01
IPC分类号： H03M13/09
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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公开(公告)号：US20090202076A1
公开(公告)日：2009-08-13
申请号：US12028953
申请日：2008-02-11
CPC分类号： H04L25/03866
摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.
摘要翻译： 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。
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33.发明授权System, method and storage medium for deriving clocks in a memory system 失效用于在存储器系统中导出时钟的系统，方法和存储介质公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 一种用于在存储器系统中导出时钟的系统，方法和存储介质。 该方法包括在集线器装置处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
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34.发明授权公开(公告)号：US07403073B2
公开(公告)日：2008-07-22
申请号：US11469423
申请日：2006-08-31
IPC分类号： H03L7/00
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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35.发明申请公开(公告)号：US20080123771A1
公开(公告)日：2008-05-29
申请号：US11557676
申请日：2006-11-08
申请人： Hayden C. Cranford , Daniel J. Friedman , James S. Mason , Martin L. Schmatz , Michael A. Sorna , Thomas H. Toifl
发明人： Hayden C. Cranford , Daniel J. Friedman , James S. Mason , Martin L. Schmatz , Michael A. Sorna , Thomas H. Toifl
CPC分类号： H04L25/0278
摘要： Systems for making impedance adjustments that will auto-tune a communication path is disclosed. The method can utilize time domain reflectometry (TDR) to acquire data about impedance mismatches and can adjust the termination impedances based on the acquired data. A system is also disclosed that has an isolator to decouple a first adjustable resistor from a transmission path in a first mode and couple the first adjustable resistor to the path in a second mode. The system can have a test transmitter to create a first current on the path in the first mode and to create a second current having twice the current in a second mode, wherein a detector can detect a first voltage during the first mode and a second voltage in the second mode as the first adjustable resistive load is adjusted in the second mode until it reaches a value matching the first voltage detected in the first mode.
摘要翻译： 公开了用于进行自动调谐通信路径的阻抗调整的系统。 该方法可以利用时域反射（TDR）获取有关阻抗不匹配的数据，并可以根据获取的数据调整终端阻抗。 还公开了一种具有隔离器的系统，用于在第一模式中将第一可调电阻器与传输路径去耦，并将第一可调电阻器以第二模式耦合到路径。 该系统可以具有测试发射器，以在第一模式中在路径上产生第一电流，并且在第二模式中产生具有两倍电流的第二电流，其中检测器可以在第一模式期间检测第一电压，而第二电压 在第二模式中，第一可调电阻负载在第二模式中被调节，直到达到与在第一模式中检测到的第一电压匹配的值。
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公开(公告)号：US07088170B2
公开(公告)日：2006-08-08
申请号：US10827783
申请日：2004-04-20
申请人： Thomas E. Morf , Martin L. Schmatz
发明人： Thomas E. Morf , Martin L. Schmatz
IPC分类号： H03K17/693 , H03K17/62
CPC分类号： H03K17/005 , G11C7/1012
摘要： The multiplexer according to the invention comprises a first data input line (TL1) for incoming data (Data 1), a second data input line (TL2) for incoming data (Data 2), and a data output line (TL3) for outgoing data (Data out). The multiplexer further comprises a control line (20, 21, 22) for applying a control signal (clk) to a first switching means (T1, T3, T5; SR1, SR3, SR5) and a second switching means (T2, T4, T6; SR2, SR4, SR6) for alternatively connecting the first data input line (TL1) over the first switching means (T1, T3, T5; SR1, SR3, SR5) and the second input line (TL2) over the second switching means (T2, T4, T6; SR2, SR4, SR6) to the data output line (TL3), wherein the first and second switching means (T1–T6; SR1–SR6) are spatially arranged in such a way, that the control signal (clk) applied to the first switching means (T1, T3, T5; SR1, SR3, SR5) compared with the control signal (clk) applied to the second switching means (T2, T4, T6; SR2, SR4, SR6) shows a phase shift.
摘要翻译： 根据本发明的多路复用器包括用于输入数据（数据1）的第一数据输入线（TL1），用于输入数据（数据2）的第二数据输入线（TL 2）和数据输出线（TL 3） 用于输出数据（Data out）。 多路复用器还包括用于向第一切换装置（T 1，T 3，T 5; SR 1，SR 3，SR 5）施加控制信号（clk）的控制线（20,21,22）和第二切换 用于将第一数据输入线（TL1）交替地连接在第一开关装置（T 1，T 3，T 5; SR 1，T 5，SR 4，SR 6）上的装置（T 2，T 4，T 6; SR 2， SR 3，SR 5）和第二输入线（TL 2）通过第二切换装置（T 2，T 4，T 6; SR 2，SR 4，SR 6）发送到数据输出线（TL 3） 第一和第二切换装置（T 1 -T 6; SR 1 -SR 6）以这样的方式空间地布置，即施加到第一切换装置的控制信号（clk）（T 1，T 3，T 5; SR2，SR4，SR6）与施加到第二开关装置（T 2，T 4，T 6; SR 2，SR 4，SR 6）的控制信号（clk）相比较，
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37.发明授权Error correcting code protected quasi-static bit communication on a high-speed bus 失效在高速总线上纠错代码保护的准静态位通信公开(公告)号：US08516338B2
公开(公告)日：2013-08-20
申请号：US13535574
申请日：2012-06-28
IPC分类号： H03M13/00
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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38.发明申请公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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39.发明授权Clock and data recovery system and method for clock and data recovery based on a forward error correction 有权基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法公开(公告)号：US07522687B2
公开(公告)日：2009-04-21
申请号：US11214161
申请日：2005-08-29
IPC分类号： H04L7/00
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).
摘要翻译： 根据本发明的基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟（sclk）触发的接收数据的数据锁存器（16）。 该系统还包括用于确定采样的接收数据是否以及哪个是错误的并且用于产生相位/频率校正信号（ctrl）的错误确定单元（20,21）。 此外，该系统包括用于根据校正信号（ctrl）产生采样时钟（sclk）的时钟发生器（23,24,25）。
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公开(公告)号：US20090039916A1
公开(公告)日：2009-02-12
申请号：US11834926
申请日：2007-08-07
IPC分类号： G06F7/38
CPC分类号： G11C7/1045 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/109
摘要： An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter.
摘要翻译： 用于存储器输入/输出（I / O）引脚的集成电路具有五种不同的操作模式。 内存芯片可以使用无缓冲（或注册）双列直插式内存模块（DIMM）以及完全缓冲的DIMM进行操作。 T型线圈电路可以均衡高速功能的电容负载。 示例性实施例提供了包含可用作电源或接地的多功能物理I / O电路的存储器芯片; 作为DDR2或DDR3接口; 作为高速差分接收机; 或作为高速差分变送器。
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