公开(公告)号：US20070194388A1

公开(公告)日：2007-08-23

申请号：US11730988

申请日：2007-04-05

申请人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L29/94

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the NMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在NMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

公开(公告)号：US06876208B2

公开(公告)日：2005-04-05

申请号：US10232689

申请日：2002-09-03

申请人： Tatsuya Kunikiyo ,  Katsumi Eikyu ,  Kyoji Yamashita ,  Katsuhiro Ohtani ,  Hiroyuki Umimoto ,  Mutsumi Kobayashi

发明人： Tatsuya Kunikiyo ,  Katsumi Eikyu ,  Kyoji Yamashita ,  Katsuhiro Ohtani ,  Hiroyuki Umimoto ,  Mutsumi Kobayashi

IPC分类号： H01L21/76 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/10 ,  H01L29/78 ,  H01L23/58 ,  G01R27/26

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1045 ,  H01L29/7801 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4′) are selectively formed in a surface of a body region (16), and extension regions (5) and (5′) are extended from tip portions of the source-drain regions (4) and (4′) opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4′) including the extension regions (5) and (5′) and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6′) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5′) and a peripheral portion of the extension region (5).

摘要翻译： 本发明的目的是获得具有可以高精度地测量电容值的用于CBCM（基于电荷的电容测量）电路的半导体器件。 构成CBCM电路的MOS晶体管具有以下结构。 更具体地，源极 - 漏极区域（4）和（4'）选择性地形成在体区域（16）的表面中，并且延伸区域（5）和（5'）从源极 - 漏极 分别相对的区域（4）和（4'）。 在包括延伸区域（5）和（5'）的源极 - 漏极区域（4）和（4'）之间形成栅极绝缘膜7，并且在栅极绝缘膜（7）上形成栅电极（8） 。 在扩展区域5（5'）的末端部分和延伸区域5（5'）的周边部分中不形成与杂质浓度高于沟道区域的常规结构中的口袋区域6（​​6'）相对应的区域 区域（5）。

公开(公告)号：US06432802B1

公开(公告)日：2002-08-13

申请号：US09662359

申请日：2000-09-15

申请人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513

摘要： After a gate electrode has been formed over a semiconductor region with a gate insulating film interposed therebetween, an amorphous layer is formed in the semiconductor region by implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask. Then, ions of a first dopant are implanted into the semiconductor region using the gate electrode as a mask. Next, a first annealing process is conducted on the semiconductor region at a temperature between 400° C. and 550° C., thereby making the amorphous layer recover into a crystalline layer. Subsequently, a second annealing process is conducted on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type. The extended high-concentration dopant diffused layer is formed to have a shallow junction by diffusing the first dopant, while the pocket dopant diffused layer is formed under the extended high-concentration dopant diffused layer by diffusing the heavy ions.

摘要翻译： 在半导体区域上形成栅极电极之后，在栅极绝缘膜之间形成栅电极之后，通过使用栅电极作为掩模，将具有大质量的重离子注入到半导体区域中，在半导体区域中形成非晶层。 然后，使用栅电极作为掩模，将第一掺杂剂的离子注入半导体区域。 接下来，在400℃〜550℃的温度下对半导体区域进行第一退火处理，由此使非晶层回复成晶体层。 随后，对半导体区域进行第二退火处理，从而形成第一导电类型的扩展高浓度掺杂剂扩散层和第二导电类型的袋式掺杂剂扩散层。 通过扩散第一掺杂剂，扩展的高浓度掺杂剂扩散层通过扩散第一掺杂剂而形成为浅结，而通过扩散重离子而在扩展的高浓度掺杂剂扩散层下方形成袋掺杂剂扩散层。

公开(公告)号：US06251718B1

公开(公告)日：2001-06-26

申请号：US09011891

申请日：1998-02-23

申请人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

发明人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

IPC分类号： H01L218238

CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/28211 ,  H01L21/324 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/105

摘要： A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900° C. to about 1100° C.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：通过离子注入形成用于控制阈值电压的杂质扩散层; 并进行高温快速热处理，以回收由离子注入产生的晶体缺陷。 更具体地说，高温快速热处理的处理条件被设定为使得晶体缺陷引起的间隙原子扩散，杂质扩散层中的杂质不扩散。 例如，高温快速热处理在约900℃至约1100℃的温度范围内进行。

公开(公告)号：US5610430A

公开(公告)日：1997-03-11

申请号：US494384

申请日：1995-06-26

申请人： Kyoji Yamashita ,  Shinji Odanaka ,  Kazumi Kurimoto ,  Hiroyuki Umimoto

发明人： Kyoji Yamashita ,  Shinji Odanaka ,  Kazumi Kurimoto ,  Hiroyuki Umimoto

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/76 ,  H01L27/088 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823857 ,  H01L29/0847 ,  H01L29/42368 ,  H01L21/26586 ,  H01L29/66545 ,  Y10S257/90

摘要： The semiconductor device of the invention includes: a semiconductor substrate of a first conductivity type; a gate insulating film formed on a selected region on a main surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; and a source region and a drain region which are formed of high-concentration impurity diffusion layers of a second conductivity type in the semiconductor substrate. In the semiconductor device, a thickness of both end portions of the gate insulating film is larger than a thickness of a center portion of the gate insulating film, and each of the source region and the drain region includes a first portion located under both end-portions of the gate insulating film and a second portion having a thickness equal to or larger than a thickness of the first portion. An impurity concentration in the first portion is substantially equal to an impurity concentration in the second portion.

摘要翻译： 本发明的半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的主表面上的选定区域上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及在半导体衬底中由第二导电类型的高浓度杂质扩散层形成的源极区和漏极区。 在半导体装置中，栅极绝缘膜的两端部的厚度大于栅极绝缘膜的中央部的厚度，源区域和漏极区域中的每一个包括位于两端部的第一部分， 栅极绝缘膜的一部分和第二部分的厚度等于或大于第一部分的厚度。 第一部分中的杂质浓度基本上等于第二部分中的杂质浓度。