公开(公告)号：US20060208319A1

公开(公告)日：2006-09-21

申请号：US11418029

申请日：2006-05-05

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/94

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US20060202286A1

公开(公告)日：2006-09-14

申请号：US11418024

申请日：2006-05-05

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/76

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

公开(公告)号：US06878703B2

公开(公告)日：2005-04-12

申请号：US10442874

申请日：2003-05-20

申请人： Toshio Sada ,  Makoto Mizuno

发明人： Toshio Sada ,  Makoto Mizuno

IPC分类号： A61K31/4178 ,  A61K31/54 ,  A61K45/06 ,  A61P9/12 ,  A61K31/41

CPC分类号： A61K45/06 ,  A61K31/4178 ,  A61K31/54 ,  A61K2300/00

摘要： A pharmaceutical composition comprises an angiotensin II receptor antagonist selected from among compounds having the following formula (I), a pharmacologically acceptable salt thereof, a pharmacologically acceptable ester thereof and a pharmacologically acceptable salt of such ester, and one or more diuretics: The pharmaceutical composition of the present invention has an excellent hypotensive effect and low toxicity, and therefore is useful as a medicament for preventing or treating hypertension or heart disease.

摘要翻译： 药物组合物包含选自具有下式（I）的化合物，其药理学上可接受的盐，其药理学可接受的酯和该药学上可接受的盐的一种或多种利尿剂的血管紧张素II受体拮抗剂：药物组合物 本发明具有优异的降血压效果和低毒性，因此可用作预防或治疗高血压或心脏病的药物。

公开(公告)号：US6049132A

公开(公告)日：2000-04-11

申请号：US893671

申请日：1997-07-11

申请人： Masanori Iwahashi ,  Makoto Mizuno ,  Koji Hanihara

发明人： Masanori Iwahashi ,  Makoto Mizuno ,  Koji Hanihara

IPC分类号： G02F1/1362 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G02F1/136277 ,  G02F1/136227 ,  H01L23/53223 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53257 ,  H01L2924/0002

摘要： In a semiconductor chip for Si chip based liquid crystal having insulating films and interconnection layers formed on a semiconductor substrate, a thin interconnection layer made of TiN/Ti having strong erosion resistance is formed on an uppermost interlayer insulating film having a flat surface to substantially expose the thin uppermost interconnection layer to the surface of the chip, the uppermost insulating film is covered with a protection film made of p-SiN and a thin insulating film having a mirror-like flat surface is formed on the uppermost interconnection layer.

摘要翻译： 在具有形成在半导体衬底上的绝缘膜和互连层的用于Si芯片的液晶的半导体芯片中，在具有平坦表面的最上层的层间绝缘膜上形成具有很强的耐腐蚀性的由TiN / Ti制成的薄互连层，以基本上露出 在芯片表面的最薄的最上层的互连层，最上层的绝缘膜被由p-SiN制成的保护膜覆盖，并且在最上层的互连层上形成了具有镜面平坦表面的薄绝缘膜。

公开(公告)号：US5391509A

公开(公告)日：1995-02-21

申请号：US164954

申请日：1993-12-10

申请人： Naoki Matsukawa ,  Makoto Mizuno ,  Katsuhiro Shimazu

发明人： Naoki Matsukawa ,  Makoto Mizuno ,  Katsuhiro Shimazu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： Impurities are introduced into a semiconductor substrate by using a gate electrode formed on the semiconductor substrate through an oxide film as a mask, and low concentration impurity regions are formed. Then, side walls are formed on the gate electrode. Next, after an insulating film is formed on the whole surface of the substrate by a CVD method, impurities are introduced by using the gate electrode and the side walls as a mask, and high concentration impurity regions are formed. Then, a thermal treatment of the substrate is performed, and after the low concentration impurity regions and the high concentration impurity regions are crystallized, an interlayer insulating film is formed.

摘要翻译： 通过使用通过氧化膜形成在半导体衬底上的栅电极作为掩模，将杂质引入到半导体衬底中，形成低浓度杂质区。 然后，在栅电极上形成侧壁。 接下来，在通过CVD法在基板的整个表面上形成绝缘膜之后，通过使用栅电极和侧壁作为掩模来引入杂质，形成高浓度杂质区。 然后，进行基板的热处理，在低浓度杂质区域和高浓度杂质区域结晶后，形成层间绝缘膜。

公开(公告)号：US4970952A

公开(公告)日：1990-11-20

申请号：US479357

申请日：1990-02-13

申请人： Imao Hiraga ,  Masamori Uchikawa ,  Makoto Mizuno

发明人： Imao Hiraga ,  Masamori Uchikawa ,  Makoto Mizuno

IPC分类号： B41K3/10 ,  B41K1/10 ,  B41K1/14

CPC分类号： B41K1/10

摘要： A date-stamping apparatus having a casing, a bridge member located at the lower end of the casing, a tension roller located above the casing and forced upwardly, an endless date-printing belt having printing letters on its outside surface and spanned between the bridge member and the tension roller, a date-belt driving wheel located within the casing at a substantially intermediate portion. The date of driving wheel has a circumferential engagement section co-operating with the belt and being contacted by the outside surface of the belt, and an electric motor intermittently energized by a timing circuit and operatively connected with the belt-driving wheel, so that stamped date is electrically adjusted.

摘要翻译： 具有壳体的日期冲压装置，位于壳体下端的桥接构件，位于壳体上方并被向上推动的张紧辊，在其外表面上具有打印字母并跨越桥的无端日历打印带 构件和张紧辊，位于壳体内的大致中间部分的日期带驱动轮。 驱动轮的日期具有与皮带合作并与皮带的外表面接触的圆周接合部分，以及由定时电路间歇地通电并与皮带驱动轮可操作地连接的电动机，使得冲压 日期电气调整。

公开(公告)号：USD268598S

公开(公告)日：1983-04-12

申请号：US206978

申请日：1980-11-14

申请人： Takeshi Mizutani ,  Makoto Mizuno

设计人： Takeshi Mizutani ,  Makoto Mizuno

公开(公告)号：US08576634B2

公开(公告)日：2013-11-05

申请号：US12764090

申请日：2010-04-20

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C11/34 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US20120313293A1

公开(公告)日：2012-12-13

申请号：US13490547

申请日：2012-06-07

申请人： Kohei Wakabayashi ,  Hideki Matsumoto ,  Fumio Sakai ,  Makoto Mizuno

发明人： Kohei Wakabayashi ,  Hideki Matsumoto ,  Fumio Sakai ,  Makoto Mizuno

IPC分类号： B28B1/14 ,  B28B13/02

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： A method of performing an imprint process on each of a plurality of shot regions of a substrate, wherein each shot region includes at least one of at least one valid chip area and at least one invalid chip area, the invalid chip area including an inhibited area in which resin coating is inhibited, the imprint process for a shot region including both the invalid chip area and the valid chip area includes coating the valid chip area of the shot region with the resin, bringing a pattern surface of a mold into contact with the resin, and curing the resin, and in the step of coating, at least the inhibited area of the invalid chip area is not coated with the resin.

摘要翻译： 一种对基板的多个拍摄区域中的每一个进行压印处理的方法，其中每个拍摄区域包括至少一个有效芯片区域和至少一个无效芯片区域中的至少一个，所述无效芯片区域包括禁止区域 在其中树脂涂层被抑制的情况下，包括无效芯片面积和有效芯片面积的射击区域的压印处理包括用树脂涂覆射出区域的有效芯片面积，使得模具的图案表面与 树脂，并固化树脂，并且在涂布步骤中，至少无效芯片区域的禁止区域未被树脂涂覆。

公开(公告)号：US08174707B2

公开(公告)日：2012-05-08

申请号：US12270287

申请日：2008-11-13

申请人： Makoto Mizuno

发明人： Makoto Mizuno

IPC分类号： G01B11/14

CPC分类号： G02B7/005 ,  G02B13/143 ,  G02B17/0657 ,  G03F7/70258

摘要： An optical element positioning apparatus of the present invention includes a moving unit including an optical element 2, a drive mechanism 100 configured to drive the moving unit, a position measuring sensor 130 configured to measure a position of the optical element 2, and an optical element controller 10 configured to control the drive mechanism 100 based on a measurement result by the position measuring sensor 130. An incident position (p point) at which a principal ray of a central field enters the optical element 2 is displaced from an optical axis of an optical system including the optical element 2, and the position measuring sensor 130 measures the incident position in an optical axis direction.

摘要翻译： 本发明的光学元件定位装置包括：移动单元，包括光学元件2，构造成驱动移动单元的驱动机构100，被配置为测量光学元件2的位置的位置测量传感器130;以及光学元件 控制器10构造成基于位置测量传感器130的测量结果来控制驱动机构100.中心场的主射线进入光学元件2的入射位置（p点）从光学元件2的光轴位移 包括光学元件2的光学系统和位置测量传感器130测量光轴方向上的入射位置。