公开(公告)号：US06566964B1

公开(公告)日：2003-05-20

申请号：US09696031

申请日：2000-10-26

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H03L7197

CPC分类号： H03L7/1976 ,  H03B21/02

摘要： Accumulator 201 accumulates data K (K: integer) for every clock and outputs a carry-out signal at the time of an overflow. Random signal generator 202 outputs a random signal for every clock. Adder 203 adds the carry-out signal and random signal to data M (M: integer), changes the frequency dividing ratio randomly and converts spurious to white noise. This makes it possible to optimally maintain the spurious characteristic, shorten the lockup time and reduce power consumption.

摘要翻译： 累加器201对每个时钟累加数据K（K：整数），并在溢出时输出进位信号。 随机信号发生器202输出每个时钟的随机信号。 加法器203将进位信号和随机信号添加到数据M（M：整数），随机地改变分频比，并将杂散变为白噪声。 这使得可以最佳地保持寄生特性，缩短锁定时间并降低功耗。

公开(公告)号：US20100272222A1

公开(公告)日：2010-10-28

申请号：US12160874

申请日：2007-01-16

申请人： Yosuke Mitani ,  Shunsuke Hirano ,  Kaoru Ishida

发明人： Yosuke Mitani ,  Shunsuke Hirano ,  Kaoru Ishida

IPC分类号： H03D3/24

CPC分类号： H03L7/1976 ,  H03C3/0908 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

摘要： Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (100) includes: a PLL unit (110), first modulation signal input means for inputting a first modulation signal to a divider (112) or a phase comparator (113) of the PLL unit (110); second modulation signal input means for DA converting the digital modulation signal in a DA converter (116) to generate an analog second modulation signal and inputting it to a voltage control oscillator (111) of the PLL unit (110); a second divider for dividing the output signal of the voltage control oscillator (111); and control means for generating a center frequency control signal, a gain control signal, and a second division ration control signal according to the channel selection signal and the control voltage inputted to the voltage control oscillator (111) and supplying them to the divider (112), the DA converter (116), and the second divider (114), respectively.

摘要翻译： 提供了能够维持宽带调制的调制精度的PLL调制电路，无线发送装置以及无线通信装置。 PLL调制电路（100）包括：PLL单元（110），用于将第一调制信号输入到PLL单元（110）的分频器（112）或相位比较器（113）的第一调制信号输入装置; 第二调制信号输入装置，用于在DA转换器（116）中转换数字调制信号，以产生模拟第二调制信号并将其输入到PLL单元（110）的压控振荡器（111）; 用于分压电压控制振荡器（111）的输出信号的第二分频器; 以及控制装置，用于根据输入到电压控制振荡器（111）的通道选择信号和控制电压产生中心频率控制信号，增益控制信号和第二分频控制信号，并将其提供给分频器（112） ），DA转换器（116）和第二分频器（114）。

公开(公告)号：US07822393B2

公开(公告)日：2010-10-26

申请号：US11963924

申请日：2007-12-24

申请人： Shunsuke Hirano ,  Takahito Miyazaki

发明人： Shunsuke Hirano ,  Takahito Miyazaki

IPC分类号： H04B1/02

CPC分类号： H04B1/525

摘要： The transmission apparatus according to the present invention can reduce transmission output noise leaking into the receiving apparatus even when the transmission apparatus is applied to wireless equipment using the W-CDMA scheme. Transmission apparatus (100) has bypass circuit (101) and bypass control circuit (103) that inputs an RF phase signal to power amplifier (14) via amplitude adjustment circuit (16) when bypass circuit (101) and power amplifier (14) are operated in non-saturation mode, and that inputs the RF phase signal to power amplifier (14) via bypass circuit (101) when power amplifier (14) is operated in saturation mode.

摘要翻译： 即使当将发送装置应用于使用W-CDMA方案的无线设备时，根据本发明的发送装置也可以减少泄漏到接收装置中的发送输出噪声。 传输装置（100）具有旁路电路（101）和旁路控制电路（103），当旁路电路（101）和功率放大器（14）为...时，通过振幅调整电路（16）将RF相位信号输入到功率放大器（14） 在非饱和模式下工作，并且当功率放大器（14）以饱和模式操作时，经由旁路电路（101）将RF相位信号输入到功率放大器（14）。

公开(公告)号：US07378918B2

公开(公告)日：2008-05-27

申请号：US11410293

申请日：2006-04-25

申请人： Shunsuke Hirano ,  Hisashi Adachi

发明人： Shunsuke Hirano ,  Hisashi Adachi

IPC分类号： H03C3/00 ,  H03L7/08 ,  H03L7/18 ,  H04B1/04

CPC分类号： H04L27/20 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

摘要： There provides a two-point modulation phase modulation apparatus capable of obtaining an RF phase modulation signal of superior modulation precision with low power consumption and a simple configuration even in the event of inputting a wide band baseband modulation signal. A differentiator (21) of the opposite characteristics to the attenuation characteristics of anti-alias filter (22) is provided at the front stage of a D/A converter (6). As a result, it is possible to sufficiently suppress an alias signal without raising the sampling frequency of the D/A converter (6) (i.e. low power consumption) using an anti-alias filter (22) of a simple configuration (i.e. low cost) with a low order for a narrower bandwidth than a PLL modulation frequency bandwidth, and it is possible to obtain an RF phase modulation signal where the entire frequency band of input digital baseband modulation signal (S1) is reflected in a superior manner.

摘要翻译： 提供了即使在输入宽带基带调制信号的情况下，也能够获得具有低功耗的优良调制精度的RF相位调制信号和简单的配置的两点调制相位调制装置。 在D / A转换器（6）的前级设置有与抗混叠滤波器（22）的衰减特性相反特性的微分器（21）。 结果，可以使用简单配置的抗混叠滤波器（22）来充分抑制混叠信号而不提高D / A转换器（6）的采样频率（即，低功耗）（即，低成本 ）具有比PLL调制频率带宽更窄的带宽的低阶，并且可以获得输入数字基带调制信号（S1）的整个频带以优异的方式反映的RF相位调制信号。

公开(公告)号：US07276985B2

公开(公告)日：2007-10-02

申请号：US11352244

申请日：2006-02-13

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H04L27/36 ,  H03C3/08 ,  H03C3/40

CPC分类号： H03F1/0222 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03F2200/331 ,  H04B1/0483

摘要： Provided is a transmission modulation apparatus, using polar modulation of two-point modulation scheme, capable of completing a timing adjustment of a BB phase modulation signal and BB amplitude modulation signal in a short time. A phase modulation section (10) that performs two-point modulation with a PLL circuit is provided with a switch (17) to make the PLL circuit open loop, and when a first delay section (5) corrects the deviation in synchronization between the BB phase modulation signal and BB amplitude modulation signal, the switch (17) is turned off to make the PLL circuit open loop.

摘要翻译： 提供一种使用两点调制方式的极性调制的传输调制装置，其能够在短时间内完成BB相位调制信号和BB振幅调制信号的定时调整。 使用PLL电路进行两点调制的相位调制部（10）设置有用于使PLL电路开环的开关（17），并且当第一延迟部（5）校正BB之间的同步偏差 相位调制信号和BB振幅调制信号，开关（17）关闭，使PLL电路开路。

公开(公告)号：US07224237B2

公开(公告)日：2007-05-29

申请号：US10531050

申请日：2004-01-08

申请人： Shunsuke Hirano ,  Yasunori Miyahara

发明人： Shunsuke Hirano ,  Yasunori Miyahara

IPC分类号： H03C3/00 ,  H03L7/06 ,  H03L27/20

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0991 ,  H03L7/1976

摘要： The invention concerns a wideband modulator using a PLL synthesizer, which can match the frequency characteristic and prevent degradation in modulation accuracy even in the presence of a variation in the manufacture of circuit components. In a wideband modulator which modulates the division ratio of a frequency divider by using a modulating signal generated by a modulating signal generator and outputs a modulated carrier signal from a VCO, calibration data from a calibration data generator are input via a selector. The amplitude value of an ac component of each modulating signal, either appearing on the output of a loop filter or demodulated by a demodulator, is converted to a digital value by way of an A/D converter. The difference between the two is detected and a control signal FCR to eliminate the difference is generated in order to correct the frequency characteristic of a PLL or a pre-distortion filter.

摘要翻译： 本发明涉及使用PLL合成器的宽带调制器，其可以匹配频率特性，并且即使在存在电路部件的制造的变化的情况下也可以防止调制精度的降低。 在通过使用由调制信号发生器产生的调制信号来调制分频器的分频比并从VCO输出调制载波信号的宽带调制器中，来自校准数据发生器的校准数据经由选择器输入。 出现在环路滤波器的输出端上或由解调器解调的每个调制信号的交流分量的振幅值通过A / D转换器转换成数字值。 检测两者之间的差异，并产生消除差异的控制信号FCR，以校正PLL或预失真滤波器的频率特性。

公开(公告)号：US07157985B2

公开(公告)日：2007-01-02

申请号：US11078704

申请日：2005-03-14

申请人： Yosuke Mitani ,  Shunsuke Hirano

发明人： Yosuke Mitani ,  Shunsuke Hirano

IPC分类号： H03C3/00

CPC分类号： H03C5/00 ,  H03C3/0916 ,  H03C3/095 ,  H03C3/0991

摘要： First and second calibration signals (308, 309) are sent to a frequency divider (102) and an adder (116) of a PLL section (100A), demodulated in a demodulator (111), filtered through a low pass filter (113) and a high pass filter (114) and thereafter sent to a modulation signal control circuit (115). The modulation signal control circuit (115) generates control information (318) in comparison with the phase and amplitude of the first and second calibration signals (308 and 309) and sends the control information (318) to a modulation control signal generator (106). Modulation control signal generator (106) holds the control information (318) and controls the values of the first modulation signal and second modulation signal sent to the frequency divider (102) and adder (116) on the based on the control information (318) held in modulation operation.

摘要翻译： 第一和第二校准信号（308,309）被发送到PLL部分（100A）的分频器（102）和加法器（116），在解调器（111）中解调，通过低通滤波器（113）滤波 ）和高通滤波器（114），然后发送到调制信号控制电路（115）。 调制信号控制电路（115）与第一和第二校准信号（308和309）的相位和幅度相比产生控制信息（318），并将控制信息（318）发送到调制控制信号发生器（106） 。 调制控制信号发生器（106）保存控制信息（318），并根据控制信息（318）控制发送到分频器（102）和加法器（116）的第一调制信号和第二调制信号的值， 举行调制操作。

公开(公告)号：US07110486B2

公开(公告)日：2006-09-19

申请号：US11333245

申请日：2006-01-18

申请人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

发明人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

IPC分类号： H03D3/24 ,  H03L7/00 ,  H03C3/06

CPC分类号： H03L7/1976

摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

公开(公告)号：US20050285688A1

公开(公告)日：2005-12-29

申请号：US11078703

申请日：2005-03-14

申请人： Shunsuke Hirano ,  Hisashi Adachi

发明人： Shunsuke Hirano ,  Hisashi Adachi

IPC分类号： H03C3/09 ,  H03L7/00

CPC分类号： H03C3/0983 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095

摘要： A phase modulation apparatus is provided whereby excellent RF phase modulation signals can be obtained even when the modulation sensitivity of a voltage controlled oscillator varies. Phase modulation apparatus 100 has: phase detector 105 that performs phase detection with respect to an RF phase modulation signal outputted from VCO 101; comparator 106 that compares the phase of the detected signal with the phase of a baseband phase modulation signal and outputs the difference between the signals; variable gain amplifier 107 that controls the gain of the baseband phase modulation signal based on the output of comparator 106 and supplies the gain-controlled baseband phase modulation signal to VCO 101. By this means, the signal level of the baseband phase modulation signal that is supplied to VCO 101 can be controlled in accordance with the modulation sensitivity of VCO 101, so that phase modulation apparatus 100 can be realized whereby excellent RF phase modulation signals even when the modulation sensitivity of VCO 101 varies.

摘要翻译： 提供一种相位调制装置，即使当压控振荡器的调制灵敏度变化时，也可以获得优异的RF相位调制信号。 相位调制装置100具有：相位检测器105，其相对于从VCO101输出的RF相位调制信号进行相位检测; 比较器106，其将检测信号的相位与基带相位调制信号的相位进行比较，并输出信号之间的差; 可变增益放大器107，其基于比较器106的输出来控制基带相位调制信号的增益，并将增益控制的基带相位调制信号提供给VCO101。 通过这种方式，可以根据VCO101的调制灵敏度来控制提供给VCO 101的基带相位调制信号的信号电平，从而可以实现相位调制装置100，从而即使在 VCO 101的调制灵敏度变化。

公开(公告)号：US06563387B2

公开(公告)日：2003-05-13

申请号：US09867348

申请日：2001-05-29

申请人： Shunsuke Hirano ,  Ryoichi Yamada ,  Yasunori Miyahara ,  Yukio Hiraoka ,  Hisashi Adachi

发明人： Shunsuke Hirano ,  Ryoichi Yamada ,  Yasunori Miyahara ,  Yukio Hiraoka ,  Hisashi Adachi

IPC分类号： H03L7087

CPC分类号： H03L7/0898 ,  H03L7/087 ,  H03L7/099 ,  H03L7/107 ,  H03L7/113 ,  H03L7/199

摘要： A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated. Since the resonant frequency of the resonant circuit is changed in response to an actual oscillation frequency of the VCO 1, the frequency synthesizer can be phase-locked at a desirable frequency. Also, since the VCO can be manufactured in the IC form, the compact VCO can be made in low cost.

摘要翻译： 频率合成器设置有预分频器2和计数器3，该预分频器2和计数器3输出具有通过对VCO 1的输出信号进行分频而产生的频率的信号; 用于对参考信号源4的参考信号的频率进行分频的参考分频器5; 以使得计数器5的输出信号与参考分频器5的输出信号之间的频率误差被检测到的频率调整装置9被执行，并且响应于该检测结果，输出这样一个信号： 在VCO 1的谐振电路中使用的电容器值或电感值被切换; 以及偏置控制装置，用于将任意电压V1施加到VCO1的控制电压端，以便当频率调节装置9工作时使电荷泵7的输出信号变为高阻抗状态。 由于谐振电路的谐振频率响应于VCO1的实际振荡频率而改变，所以频率合成器可以以期望的频率锁相。 此外，由于可以以IC形式制造VCO，所以可以以低成本制造紧凑型VCO。