公开(公告)号：US06728526B2

公开(公告)日：2004-04-27

申请号：US09794185

申请日：2001-02-26

申请人： Ryoichi Yamada ,  Shunsuke Hirano ,  Yasunori Miyahara ,  Hisashi Adachi ,  Hisashi Takahashi ,  Hiroki Kojima

发明人： Ryoichi Yamada ,  Shunsuke Hirano ,  Yasunori Miyahara ,  Hisashi Adachi ,  Hisashi Takahashi ,  Hiroki Kojima

IPC分类号： H04B106

CPC分类号： H03L7/1976

摘要： A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit (5) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.

摘要翻译： 一种频率合成器装置，包括PLL电路（9）和分频比控制电路（5）。 PLL电路（9）包括相位比较器（1），低通滤波器（2），压控振荡器（3）和可变分频器（4）。 分频比控制电路（5）控制可变分频器（4），使得可变分频器（4）的分频比在时间上变化，并且分频比的时间平均值包含低于 小数点。 使用分频比控制电路（5）中的可变分频器（4）的输出信号fdiv和通过延迟元件（10）获得的输出fdiv2的两个不同信号作为累加器部分（81）的时钟， 。 可以减小由分频比控制电路（5）的操作产生的基板电位的变化和电源电压的变化，并且可以抑制频率合成器的C / N的劣化。

公开(公告)号：US06871055B2

公开(公告)日：2005-03-22

申请号：US10218658

申请日：2002-08-15

申请人： Shunsuke Hirano ,  Yasunori Miyahara

发明人： Shunsuke Hirano ,  Yasunori Miyahara

IPC分类号： H04B1/30 ,  H04B1/10

CPC分类号： H04B1/30

摘要： In a direction conversion receiver, a quadrature demodulator produces differential signals in a baseband on the basis of a local signal of a frequency synthesizer, with the differential signals being inputted through a first low pass filter, a gain control amplifier and an amplifier to a control unit and a direct current component between the differential signals being extracted in a second low pass filter. In addition, an offset compensating section reduces an offset voltage while the control unit outputs a control signal for the control of the gain control amplifier. The second low pass filter includes a time constant circuit for determining a time constant through the use of resistors and a capacitor, and a time constant changing section. A time constant control unit controls the time constant changing section for a predetermined period of time after the control unit outputs data for the change of a frequency of the local signal so that the time constant of the time constant circuit decreases. This shortens the time needed for the settlement of automatic gain control and prevents the deterioration of demodulation accuracy during a call.

摘要翻译： 在方向转换接收机中，正交解调器基于频率合成器的本地信号在基带中产生差分信号，差分信号通过第一低通滤波器，增益控制放大器和放大器输入到控制器 单元和在第二低通滤波器中提取的差分信号之间的直流分量。 此外，偏移补偿部分减小偏移电压，同时控制单元输出用于控制增益控制放大器的控制信号。 第二低通滤波器包括用于通过使用电阻器和电容器来确定时间常数的时间常数电路和时间常数变化部分。 时间常数控制单元在控制单元输出用于改变本地信号的频率的数据之后的预定时间段来控制时间常数变化部分，使得时间常数电路的时间常数减小。 这缩短了自动增益控制结算所需的时间，并防止了通话过程中解调精度的恶化。

公开(公告)号：US20060055466A1

公开(公告)日：2006-03-16

申请号：US10531050

申请日：2004-01-08

申请人： Shunsuke Hirano ,  Yasunori Miyahara

发明人： Shunsuke Hirano ,  Yasunori Miyahara

IPC分类号： H03L7/00

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0991 ,  H03L7/1976

摘要： An object of the invention is to provide wideband modulator using a PLL synthesizer which can match the frequency characteristic and prevent degradation in modulation accuracy even in the presence of a variation in the manufacture of circuit components. In a wideband modulator which modulates the division ratio of a frequency divider by using a modulating signal generated by a modulating signal generator and outputs a modulated carrier signal from a VCO, first and second calibration data from a calibration data generator are input via a selector. The amplitude value of an ac component of each modulating signal appearing on the output of a loop filter or the amplitude value of an ac component of each modulating signal demodulated by a demodulator is converted to a digital value by way of an AID converter. The difference between the two is detected by error detection means and a control signal FCR to eliminate the difference is generated by frequency characteristic correction means in order to correct the frequency characteristic of a PLL or a pre-distortion filter.

摘要翻译： 本发明的目的是提供一种使用PLL合成器的宽带调制器，其可以匹配频率特性，并且即使在存在电路部件制造的变化的情况下也能防止调制精度的降低。 在通过使用由调制信号发生器产生的调制信号来调制分频器的分频比并从VCO输出调制的载波信号的宽带调制器中，经由选择器输入来自校准数据发生器的第一和第二校准数据。 出现在环路滤波器的输出上的每个调制信号的交流分量的振幅值或由解调器解调的每个调制信号的交流分量的振幅值通过AID转换器转换成数字值。 通过误差检测装置和控制信号FCR检测两者之间的差异，以消除由频率特性校正装置产生的差异，以便校正PLL或预失真滤波器的频率特性。

公开(公告)号：US07224237B2

公开(公告)日：2007-05-29

申请号：US10531050

申请日：2004-01-08

申请人： Shunsuke Hirano ,  Yasunori Miyahara

发明人： Shunsuke Hirano ,  Yasunori Miyahara

IPC分类号： H03C3/00 ,  H03L7/06 ,  H03L27/20

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0991 ,  H03L7/1976

摘要： The invention concerns a wideband modulator using a PLL synthesizer, which can match the frequency characteristic and prevent degradation in modulation accuracy even in the presence of a variation in the manufacture of circuit components. In a wideband modulator which modulates the division ratio of a frequency divider by using a modulating signal generated by a modulating signal generator and outputs a modulated carrier signal from a VCO, calibration data from a calibration data generator are input via a selector. The amplitude value of an ac component of each modulating signal, either appearing on the output of a loop filter or demodulated by a demodulator, is converted to a digital value by way of an A/D converter. The difference between the two is detected and a control signal FCR to eliminate the difference is generated in order to correct the frequency characteristic of a PLL or a pre-distortion filter.

摘要翻译： 本发明涉及使用PLL合成器的宽带调制器，其可以匹配频率特性，并且即使在存在电路部件的制造的变化的情况下也可以防止调制精度的降低。 在通过使用由调制信号发生器产生的调制信号来调制分频器的分频比并从VCO输出调制载波信号的宽带调制器中，来自校准数据发生器的校准数据经由选择器输入。 出现在环路滤波器的输出端上或由解调器解调的每个调制信号的交流分量的振幅值通过A / D转换器转换成数字值。 检测两者之间的差异，并产生消除差异的控制信号FCR，以校正PLL或预失真滤波器的频率特性。

公开(公告)号：US06563387B2

公开(公告)日：2003-05-13

申请号：US09867348

申请日：2001-05-29

申请人： Shunsuke Hirano ,  Ryoichi Yamada ,  Yasunori Miyahara ,  Yukio Hiraoka ,  Hisashi Adachi

发明人： Shunsuke Hirano ,  Ryoichi Yamada ,  Yasunori Miyahara ,  Yukio Hiraoka ,  Hisashi Adachi

IPC分类号： H03L7087

CPC分类号： H03L7/0898 ,  H03L7/087 ,  H03L7/099 ,  H03L7/107 ,  H03L7/113 ,  H03L7/199

摘要： A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated. Since the resonant frequency of the resonant circuit is changed in response to an actual oscillation frequency of the VCO 1, the frequency synthesizer can be phase-locked at a desirable frequency. Also, since the VCO can be manufactured in the IC form, the compact VCO can be made in low cost.

摘要翻译： 频率合成器设置有预分频器2和计数器3，该预分频器2和计数器3输出具有通过对VCO 1的输出信号进行分频而产生的频率的信号; 用于对参考信号源4的参考信号的频率进行分频的参考分频器5; 以使得计数器5的输出信号与参考分频器5的输出信号之间的频率误差被检测到的频率调整装置9被执行，并且响应于该检测结果，输出这样一个信号： 在VCO 1的谐振电路中使用的电容器值或电感值被切换; 以及偏置控制装置，用于将任意电压V1施加到VCO1的控制电压端，以便当频率调节装置9工作时使电荷泵7的输出信号变为高阻抗状态。 由于谐振电路的谐振频率响应于VCO1的实际振荡频率而改变，所以频率合成器可以以期望的频率锁相。 此外，由于可以以IC形式制造VCO，所以可以以低成本制造紧凑型VCO。

公开(公告)号：US07826811B2

公开(公告)日：2010-11-02

申请号：US11594979

申请日：2006-11-09

申请人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

IPC分类号： H04B1/16

CPC分类号： H04L27/2092 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C5/00

摘要： A two-point modulation type phase apparatus and a wireless communication apparatus capable of achieving a reduction in circuit scale and low power consumption while maintaining modulation precision. It is possible to provide a D/A converter (150) that converts the inputted digital baseband signal to an analog signal, an adder (110) that adds an output signal of a D/A converter (150) and an output of a loop filter (135) to output to a control voltage terminal of the voltage controlled oscillator (105), and a peak control section (140) provided at a front stage of the D/A converter (150) that carries out smoothing of peak portions appearing at the inputted digital baseband signal, at a two-point modulation type phase modulation apparatus (100) that modulates a-carrier frequency signal using an inputted digital baseband signal by setting a frequency dividing ratio of a frequency divider (115) of a PLL circuit based on an inputted digital baseband modulation signal, and adding a voltage corresponding to a signal that is an inputted digital baseband signal analog-converted for supply to a control voltage terminal of a voltage controlled oscillator (105).

摘要翻译： 一种两点调制型相位装置和无线通信装置，其能够在保持调制精度的同时实现电路规模的降低和低功耗。 可以提供将输入的数字基带信号转换为模拟信号的D / A转换器（150），将D / A转换器（150）的输出信号和循环的输出相加的加法器（110） 滤波器（135）输出到压控振荡器（105）的控制电压端，以及峰值控制部（140），设置在D / A转换器（150）的前级，其执行出现峰值部分的平滑化 在输入的数字基带信号的两点调制型相位调制装置（100）中，通过设定PLL电路的分频器（115）的分频比，使用输入的数字基带信号来调制a载波频率信号 基于输入的数字基带调制信号，并将与作为模拟转换的输入数字基带信号的信号相对应的电压相加，供给压控振荡器（105）的控制电压端。

公开(公告)号：US20100073095A1

公开(公告)日：2010-03-25

申请号：US12566347

申请日：2009-09-24

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H03L7/085

CPC分类号： H03L7/18 ,  H03L7/085 ,  H03L7/185 ,  H03L2207/12

摘要： A frequency synthesizer (100) can selectively set an output band of VCO, and consumes less power. The frequency synthesizer (100) has a frequency converting circuit (110) that has a mixer (111) and a frequency divider (112) connected with each other in parallel. The frequency synthesizer (100) uses the frequency divider (112) upon frequency band selection in VCO (101) and uses the mixer (111) upon transmission.

摘要翻译： 频率合成器（100）可以选择性地设置VCO的输出频带，并且消耗更少的功率。 频率合成器（100）具有频率转换电路（110），其具有并联连接的混频器（111）和分频器（112）。 频率合成器（100）在VCO（101）中进行频带选择时使用分频器（112），并且在发送时使用混频器（111）。

公开(公告)号：US07236063B2

公开(公告)日：2007-06-26

申请号：US10539426

申请日：2004-07-22

申请人： Taketoshi Ochi ,  Shunsuke Hirano

发明人： Taketoshi Ochi ,  Shunsuke Hirano

IPC分类号： H03B5/00

CPC分类号： H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

摘要： A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

摘要翻译： 本发明的一个问题是以低成本提供具有良好调制精度的宽带调制PLL。 对于具有VCO（21），分频器（22），相位比较器（23），电荷泵（24）和环路滤波器（25）的PLL，VCO（21）和分频比 控制分频器（22）进行调制。 VCO（21）具有用于PLL和调制的两个控制端子，并且控制信号生成部件（28）基于相位调制数据和输入端产生VCO（21）的控制电压V tm 电压V L1到PLL的控制端子。 在调整调制因子时，控制用于调制VCO（21）的控制端子的控制电压V SUB，并且输入电压V SUB1是 并且计算VCO（21）的频率到V tm的调制灵敏度，并且基于所获得的调制灵敏度来调整相位调制数据的调制系数。

公开(公告)号：US20060115036A1

公开(公告)日：2006-06-01

申请号：US11333245

申请日：2006-01-18

申请人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

发明人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

IPC分类号： H03D3/24

CPC分类号： H03L7/1976

摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

摘要翻译： 包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。 加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。 量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。 量化数据用作受控分数部分的数据。 乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。 分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。

公开(公告)号：US20050271159A1

公开(公告)日：2005-12-08

申请号：US11080680

申请日：2005-03-16

申请人： Hiroyuki Yoshikawa ,  Hisashi Adachi ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Hisashi Adachi ,  Shunsuke Hirano

IPC分类号： H03C3/00 ,  H03C3/09 ,  H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC分类号： H03C3/0933 ,  H03C3/0925 ,  H04L27/12 ,  H04L27/2003

摘要： A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M−1 and K2=K1+1 when K1

摘要翻译： 频率调制装置100具有合成器101，微分器102，其对相位调制数据进行微分并产生差分相位调制数据;加法器103，将差分相位调制数据和载波频率数据小数部分K相加，生成加法分数部分K 1 ，接收加法分数部分K 1和载波频率数据整数部分M的输入数据操作部分104产生整数部分输入数据M 1和小数部分输入数据K 2，并向合成器101提供分数部分输入数据K 2，以及 整数部分数据延迟部分105，其在将整数部分输入数据M 1提供给合成器101之前将其延迟。 当K 1 <0时，输入数据运算部104使M 1 = M-1，K 2 = K 1 +1，当0 <= K 1 <1时，M 1 = M，K 2 = K 1，使M 1 = 1 + = 1，K 2 = K 1 -1。