公开(公告)号：US09135966B2

公开(公告)日：2015-09-15

申请号：US13566779

申请日：2012-08-03

申请人： Hisashi Iwamoto ,  Yuji Yano ,  Kazunari Inoue

发明人： Hisashi Iwamoto ,  Yuji Yano ,  Kazunari Inoue

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C7/1069 ,  G11C7/1006 ,  G11C7/1096 ,  G11C7/222

摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

摘要翻译： 半导体器件包括多个存储器阵列和多个存储器阵列控制电路。 多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路 读/写控制电路。

公开(公告)号：US06338113B1

公开(公告)日：2002-01-08

申请号：US09195037

申请日：1998-11-19

申请人： Takashi Kubo ,  Kenichi Yasuda ,  Hisashi Iwamoto

发明人： Takashi Kubo ,  Kenichi Yasuda ,  Hisashi Iwamoto

IPC分类号： G06F1202

CPC分类号： G06F13/1684

摘要： There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

摘要翻译： 提供了存储器控制器，多个存储器模块和多个存储器模块公共的外部数据总线。 多个存储器模块各自包括多个存储器芯片，连接在对应的存储器芯片和输入/输出端子之间的多个内部数据总线，逻辑芯片和多个开关晶体管，每个开关晶体管连接在相应的内部数据总线 以及相应的输入/输出端子，以响应于来自逻辑芯片的控制信号而导通/截止。 由存储器控制器选择的存储器模块中的多个开关晶体管导通，并且除了选择的存储器模块之外的存储器模块中的多个开关晶体管截止。 因此，可以在保持高速数据传输的同时增加存储器模块的容量。

公开(公告)号：US06170036A

公开(公告)日：2001-01-02

申请号：US08780066

申请日：1996-12-23

申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC分类号： G06F1300

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C7/103 ,  G11C7/1045 ,  G11C11/005 ,  G11C2207/2254

摘要： A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

摘要翻译： 半导体存储器件被配置为包括静态随机存取存储器（SRAM）阵列和动态随机存取存储器（DRAM）阵列。 存储器件包括内部数据线，其能够在SRAM和DRAM阵列之间传输数据块。 数据传输电路与内部数据线分开提供，并且包括用于锁存要传送的数据的锁存电路。 数据传输电路响应传输指定信号。

公开(公告)号：US6052329A

公开(公告)日：2000-04-18

申请号：US120031

申请日：1998-07-21

申请人： Aiko Nishino ,  Hisashi Iwamoto

发明人： Aiko Nishino ,  Hisashi Iwamoto

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1072

摘要： An output circuit and a synchronous semiconductor memory device according to the invention suppress output of invalid data, and perform data output with exact timings. The synchronous semiconductor memory device includes a plurality of output buffers provided correspondingly to data I/O terminals, a plurality of data transfer latch circuits and a plurality of output control signal latch circuits. Data transfer latch circuit transfers data read from a memory cell to the corresponding output buffer in response to an internal clock signal. The output control signal latch circuit issues an output control signal to the corresponding output buffer in synchronization with the internal clock signal. Thereby, an output timing of each output buffer can be controlled independently of the other output buffer.

摘要翻译： 根据本发明的输出电路和同步半导体存储器件抑制无效数据的输出，并以精确的定时执行数据输出。 同步半导体存储器件包括与数据I / O端子相对应设置的多个输出缓冲器，多个数据传输锁存电路和多个输出控制信号锁存电路。 数据传输锁存电路响应于内部时钟信号将从存储器单元读取的数据传送到相应的输出缓冲器。 输出控制信号锁存电路与内部时钟信号同步地向对应的输出缓冲器发出输出控制信号。 因此，可以独立于另一个输出缓冲器来控制每个输出缓冲器的输出定时。

公开(公告)号：US6026029A

公开(公告)日：2000-02-15

申请号：US865310

申请日：1997-05-29

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5946266A

公开(公告)日：1999-08-31

申请号：US946650

申请日：1997-10-07

申请人： Hisashi Iwamoto ,  Yasuhiro Konishi

发明人： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： In a synchronous dynamic random access memory (SDRAM), one bank A is divided into banks A0 and A1, and two sets of writing-related circuits are arranged corresponding to each memory cell array bank and are capable of performing writing operation substantially independently. The first and second bits of write data applied successively from the outside world are applied alternately to write registers. Since the I/O line pair is connected to the selected memory cells in respective memory cell array banks after incorporation of the second bit data to be written is completed, the potential levels of the corresponding I/O line pair always change to the corresponding potential levels from the initial state in writing the first and second bit data.

摘要翻译： 在同步动态随机存取存储器（SDRAM）中，一组A分为存储体A0和A1，并且对应于每个存储单元阵列组布置两组写相关电路，并且能够基本上独立地执行写操作。 从外部连续应用的写入数据的第一和第二位被交替地应用于写入寄存器。 由于在结合待写入的第二位数据结束之后I / O线对连接到相应存储单元阵列组中的所选存储单元，所以相应I / O线对的电位电平总是变为相应的电位 从初始状态写入第一和第二位数据的电平。

公开(公告)号：US5892730A

公开(公告)日：1999-04-06

申请号：US980963

申请日：1997-12-01

申请人： Nobuyuki Sato ,  Hisashi Iwamoto

发明人： Nobuyuki Sato ,  Hisashi Iwamoto

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1072

摘要： A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.

摘要翻译： 同步半导体存储器件可以使用一个芯片实现流水线模式和预取模式中的任一种。 根据存储在模式寄存器中的CAS（列地址选通）等待时间4指令信号MCL4，将来自控制信号发生电路的控制信号的生成序列设置为流水线模式或预取模式。 模式切换电路仅根据CAS延迟来切换写缓冲器的复位定时。 因此，可以根据操作环境容易地切换内部数据写入模式，并且同步半导体存储器件可以利用一个芯片实现多个数据写入模式。

公开(公告)号：US5867446A

公开(公告)日：1999-02-02

申请号：US332626

申请日：1994-10-31

申请人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

公开(公告)号：US5848004A

公开(公告)日：1998-12-08

申请号：US625578

申请日：1996-03-28

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5603009A

公开(公告)日：1997-02-11

申请号：US356046

申请日：1994-12-14

申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G06F13/00 ,  G11C11/34

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C11/005 ,  G11C7/103 ,  G11C7/1045 ,  G11C2207/2254

摘要： A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.

摘要翻译： 包含高速缓存的半导体存储器件包括作为高速缓冲存储器的静态随机存取存储器（SRAM）和作为主存储器的动态随机存取存储器（DRAM）。 通过双向数据传输门电路和内部数据线，可以在DRAM和SRAM之间进行数据块的集中传输。 在DRAM中提供DRAM行解码器和DRAM列解码器。 在SRAM中提供SRAM行解码器和SRAM列解码器。 SRAM和DRAM的地址可以独立应用。 数据传输门包括一个锁存电路，用于锁存来自用作高速存储器的SRAM的数据，放大器电路和用于放大来自DRAM的数据的门电路，其用作大容量存储器，并用于发送放大 数据到SRAM，以及门电路，响应于用于将写入数据发送到DRAM的相应存储器单元的DRAM写使能信号。 在SRAM的数据被锁存电路锁存之后，写入数据从门电路传输到DRAM，写数据通过放大电路和门电路传输到SRAM。