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    ID generation apparatus and method for serially interconnected devices
    31.
    发明授权
    ID generation apparatus and method for serially interconnected devices 有权
    用于串行互连设备的ID产生设备和方法

    公开(公告)号：US08984249B2

    公开(公告)日：2015-03-17

    申请号：US11613563

    申请日：2006-12-20

    申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Steven Przybylski

    发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Steven Przybylski

    IPC分类号： G06F12/00 ,  G11C7/20 ,  G06F13/42 ,  G11C7/10 ,  G11C19/00 ,  G11C29/44

    CPC分类号： G11C7/20 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1003 ,  G11C19/00 ,  G11C2029/4402

    摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

    摘要翻译： 多个存储器件（例如，DRAM，SRAM，NAND闪存，NOR闪存）被串联连接。 每个互连设备接收设备标识符（ID）并将其锁定为其ID。 每个设备包括用于计算另一个ID或增加的ID以生成它的电路。 生成的ID被传送到另一个设备，并且ID在串行互连中的每个设备中增加。 互连中的最后一个设备提供最后生成的ID，其提供给具有从所提供的最后生成的ID识别串行互连设备的总数的识别电路的存储器控​​制器。 识别电路识别串行互连中设备的总输出延迟。

    System and method of operating memory devices of mixed type
    33.
    发明授权
    System and method of operating memory devices of mixed type 有权
    操作混合型存储器件的系统和方法

    公开(公告)号：US08819377B2

    公开(公告)日：2014-08-26

    申请号：US13038997

    申请日：2011-03-02

    申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4239 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/30

    摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

    摘要翻译： 提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。 存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。 每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。 每个存储器命令特定于目标存储器件的存储器类型。 存储器命令和存储器响应的数据路径由互连提供。 给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。 在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。 存储器响应被传送到存储器控制器。

    Address assignment and type recognition of serially interconnected memory devices of mixed type
    34.
    发明授权
    Address assignment and type recognition of serially interconnected memory devices of mixed type 失效
    混合型串行互连存储器件的地址分配和类型识别

    公开(公告)号：US08433874B2

    公开(公告)日：2013-04-30

    申请号：US11771023

    申请日：2007-06-29

    申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G06F12/00

    CPC分类号： G11C7/20 ,  G06F12/0653 ,  G06F13/1694 ,  G11C7/10 ,  G11C8/12 ,  G11C8/18

    摘要： A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and an input serial interface for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, flash memory (e.g., NAND- and NOR-type flash memories). In an initialization phase, the memory devices are assigned with consecutive number addresses. The memory controller sends a target address and can recognize the type of the targeted memory device. A data path for the memory commands and the memory responses is provided by the interconnection.

    摘要翻译： 提供了存储器系统架构，其中存储器控制器控制串行互连配置中的存储器件的操作。 存储器控制器具有用于发送存储器命令的输出串行接口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入串行接口。 每个存储器件包括存储器，例如闪速存储器（例如NAND和NOR型闪速存储器）。 在初始化阶段，存储器设备被分配有连续的地址。 存储器控制器发送目标地址并且可以识别目标存储器件的类型。 存储器命令和存储器响应的数据路径由互连提供。

    Apparatus and method for establishing device identifiers for serially interconnected devices
    36.
    发明授权
    Apparatus and method for establishing device identifiers for serially interconnected devices 失效
    用于建立串行互连设备的设备标识符的设备和方法

    公开(公告)号：US08335868B2

    公开(公告)日：2012-12-18

    申请号：US11750649

    申请日：2007-05-18

    申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

    发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

    IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/4291

    摘要： A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.

    摘要翻译： 一种方法或设备操作串行互连配置中的多个设备以建立每个设备的设备标识符（ID）。 输入信号通过使用也由第一设备用于输入其它信息（例如，数据，命令，控制信号）的输入通过串行互连传输到第一设备。 发生电路响应于输入信号产生装置ID。 传输电路然后通过第一设备的串行输出将与设备ID相关联的输出信号传送到第二设备。 串行输出也由第一设备用于在串行互连配置中向另一设备输出其他信息（例如，信号，数据）。

    Bridge device architecture for connecting discrete memory devices to a system
    37.
    发明授权
    Bridge device architecture for connecting discrete memory devices to a system 有权
    用于将分立存储器件连接到系统的桥接器件架构

    公开(公告)号：US08134852B2

    公开(公告)日：2012-03-13

    申请号：US12533732

    申请日：2009-07-31

    申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

    摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接到至少一个分立存储器件的本地控制接口，用于连接到至少一个分立存储器件的本地输入/输出接口以及插入本地控制接口和 本地输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

    Apparatus and method for using a page buffer of a memory device as a temporary cache
    39.
    发明授权
    Apparatus and method for using a page buffer of a memory device as a temporary cache 失效
    使用存储器件的页缓冲器作为临时缓存的装置和方法

    公开(公告)号：US08046527B2

    公开(公告)日：2011-10-25

    申请号：US12029634

    申请日：2008-02-12

    申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

    发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

    CPC分类号： G06F13/4243 ,  G06F13/4247

    摘要： An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.

    摘要翻译： 提供了一种使用存储器件的页缓冲器作为数据的临时缓存的装置和方法。 存储器控制器将数据写入页缓冲器，并且随后读出数据而不将数据编程到存储器件的存储单元中。 这允许存储器控制器使用页面缓冲器作为临时缓存，使得数据不必占用存储器控制器的本地数据存储元件中的空间。 因此，存储器控制器可以将其自己的存储元件中的空间用于其他操作。