DE-Embedding Method For On-Wafer Devices
    31.
    发明申请
    DE-Embedding Method For On-Wafer Devices 有权
    晶圆设备的嵌入方法

    公开(公告)号:US20090224791A1

    公开(公告)日:2009-09-10

    申请号:US12042606

    申请日:2008-03-05

    IPC分类号: G01R31/27

    CPC分类号: G01R31/2884 H01L22/34

    摘要: A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

    摘要翻译: 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件(“DUT”)的固有特性的一组参数。

    Method and apparatus for de-embedding on-wafer devices
    32.
    发明授权
    Method and apparatus for de-embedding on-wafer devices 有权
    用于去嵌入晶片装置的方法和装置

    公开(公告)号:US07954080B2

    公开(公告)日:2011-05-31

    申请号:US12042606

    申请日:2008-03-05

    IPC分类号: G06F17/50

    CPC分类号: G01R31/2884 H01L22/34

    摘要: A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

    摘要翻译: 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件(“DUT”)的固有特性的一组参数。

    Meander line resistor structure
    33.
    发明授权
    Meander line resistor structure 有权
    曲折线电阻结构

    公开(公告)号:US08890222B2

    公开(公告)日:2014-11-18

    申请号:US13365303

    申请日:2012-02-03

    IPC分类号: H01L27/108 H01L29/8605

    摘要: A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor.

    摘要翻译: 弯曲线电阻器结构包括形成在第一有源区上的第一电阻器,其中第一电阻器由串联连接的多个第一通孔形成,第二电阻器形成在第二有源区上,其中第二电阻器由 串联连接的多个第二通孔和形成在第二有源区上的第三电阻器,其中第三电阻器由串联连接的多个第三通孔形成。 曲折线电阻器还包括耦合在第一电阻器和第二电阻器之间的第一连接器。

    Integrated circuit ground shielding structure
    36.
    发明授权
    Integrated circuit ground shielding structure 有权
    集成电路接地屏蔽结构

    公开(公告)号:US08659126B2

    公开(公告)日:2014-02-25

    申请号:US13313240

    申请日:2011-12-07

    IPC分类号: H01L23/552

    摘要: The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译: 本公开提供了一种集成电路(IC)装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽(PGS)结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。

    Meander Line Resistor Structure
    37.
    发明申请
    Meander Line Resistor Structure 有权
    曲折线电阻器结构

    公开(公告)号:US20130200448A1

    公开(公告)日:2013-08-08

    申请号:US13365303

    申请日:2012-02-03

    摘要: A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor.

    摘要翻译: 弯曲线电阻器结构包括形成在第一有源区上的第一电阻器,其中第一电阻器由串联连接的多个第一通孔形成,第二电阻器形成在第二有源区上,其中第二电阻器由 串联连接的多个第二通孔和形成在第二有源区上的第三电阻器,其中第三电阻器由串联连接的多个第三通孔形成。 曲折线电阻器还包括耦合在第一电阻器和第二电阻器之间的第一连接器。

    INDUCTORS WITH THROUGH VIAS
    38.
    发明申请
    INDUCTORS WITH THROUGH VIAS 有权
    电导通过VIAS

    公开(公告)号:US20130154053A1

    公开(公告)日:2013-06-20

    申请号:US13330127

    申请日:2011-12-19

    IPC分类号: H01L27/08 H01L21/02

    摘要: A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.

    摘要翻译: 提供一种使用具有一个或多个通孔的电感器的装置,以及制造方法。 在一个实施例中,在一个或多个金属化层中形成电感器。 一个或多个通孔位于电感器正下方。 通孔可以延伸穿过介于衬底和电感器之间的一个或多个电介质层。 此外,通孔可以完全地或部分地延伸通过衬底。

    Inductors with through VIAS
    40.
    发明授权
    Inductors with through VIAS 有权
    通过VIAS的电感器

    公开(公告)号:US08580647B2

    公开(公告)日:2013-11-12

    申请号:US13330127

    申请日:2011-12-19

    IPC分类号: H01L21/20

    摘要: A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.

    摘要翻译: 提供一种使用具有一个或多个通孔的电感器的装置,以及制造方法。 在一个实施例中,在一个或多个金属化层中形成电感器。 一个或多个通孔位于电感器正下方。 通孔可以延伸穿过介于衬底和电感器之间的一个或多个电介质层。 此外,通孔可以完全地或部分地延伸通过衬底。