Apparatus and method to tolerate floating input pin for input buffer
    32.
    发明授权
    Apparatus and method to tolerate floating input pin for input buffer 有权
    允许输入缓冲器的浮动输入引脚的装置和方法

    公开(公告)号:US08400190B2

    公开(公告)日:2013-03-19

    申请号:US12565624

    申请日:2009-09-23

    IPC分类号: H03K3/00

    摘要: An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

    摘要翻译: 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管,连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路,所述电路包括反馈晶体管,所述反馈晶体管具有电耦合到所述焊盘的控制端子,电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

    APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES
    34.
    发明申请
    APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES 有权
    用于检测存储器件中的字线泄漏的装置和方法

    公开(公告)号:US20090063918A1

    公开(公告)日:2009-03-05

    申请号:US11845690

    申请日:2007-08-27

    IPC分类号: G11C29/08

    摘要: A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines.

    摘要翻译: 一种用于检测存储器件中的字线泄漏的方法,包括:将所述存储器件中的第一多个字线耦合到电压源,同时接地第二多个字线。 第二多个字线中的每一个与第一多个字线中的相应一个字线相邻。 该方法包括等待一段时间以允许字线达到预定的读取电压电平。 该方法还包括将第一多个字线与电压源去耦,并等待第二预定时间段以允许第一个多个字线放电。 该方法还包括感测与字线相关联的电流,以及将电流与为了识别与第一多个字线相关联的字线泄漏状况而被选择的预定参考电流进行比较。

    Memory device having a virtual ground array and methods using program algorithm to improve read margin loss
    37.
    发明申请
    Memory device having a virtual ground array and methods using program algorithm to improve read margin loss 有权
    具有虚拟接地阵列的存储器件和使用程序算法的方法来改善读取容差损失

    公开(公告)号:US20060109710A1

    公开(公告)日:2006-05-25

    申请号:US11273120

    申请日:2005-11-14

    IPC分类号: G11C16/06

    摘要: A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

    摘要翻译: 具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。 如果确定泄漏电流通过一个或多个相邻存储器单元,则基于第一阈值状态来验证编程存储器单元。 如果泄漏电流未被确定通过一个或多个相邻存储器单元,则基于第二阈值状态来验证编程存储器单元。

    Method for tracking metal bit line coupling effect
    39.
    发明授权
    Method for tracking metal bit line coupling effect 有权
    跟踪金属位线耦合效应的方法

    公开(公告)号:US06385097B1

    公开(公告)日:2002-05-07

    申请号:US09805192

    申请日:2001-03-14

    IPC分类号: G11C700

    CPC分类号: G11C7/1051 G11C7/06 G11C7/14

    摘要: A method for tracking metal bit line coupling effect in sensing a signal received from an array cell within a memory array is disclosed. The method includes that a reference unit with a reference cell is provided, wherein the reference unit induces coupling effect. Then, the memory array and the reference unit are charged to generate a cell signal having coupling effect and a reference signal having coupling effect. Next, a sensing signal is generated from the difference of the cell signal and the reference signal, whereby the coupling effect is compensated. In the read-out operation of the present invention, because of the closeness of two adjacent metal bit lines, the coupling effect is induced in both memory array and reference unit at the same time, so that the coupling effect is compensated. Therefore, precise read-out operation of data stored in a memory cell is made possible, and the reliability of the device is improved by the present invention.

    摘要翻译: 公开了一种用于跟踪金属位线耦合效应以感测从存储器阵列内的阵列单元接收的信号的方法。 该方法包括提供具有参考单元的参考单元,其中参考单元引起耦合效应。 然后,对存储器阵列和参考单元进行充电以产生具有耦合效应的单元信号和具有耦合效应的参考信号。 接下来,从单元信号和参考信号的差产生感测信号,从而补偿耦合效果。 在本发明的读出操作中,由于两个相邻的金属位线的接近,同时在存储器阵列和参考单元两者中引起耦合效应,从而补偿耦合效应。 因此,存储在存储单元中的数据的精确读出操作成为可能,并且通过本发明提高了器件的可靠性。

    Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change
    40.
    发明授权
    Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change 有权
    电压升压发生器,用于减少由于工作电压变化和温度变化引起的影响

    公开(公告)号:US06580287B2

    公开(公告)日:2003-06-17

    申请号:US10099806

    申请日:2002-03-13

    IPC分类号: H03K19003

    CPC分类号: H02M3/07

    摘要: A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.

    摘要翻译: 一种电压升压发生器,用于降低由于工作电压变化和温度变化引起的影响。 发电机包括延迟线电路和升压电路。 延迟线电路用于根据初始升压信号执行时间延迟并产生控制信号。 升压电路根据控制信号用于升压。