公开(公告)号：US08652891B1

公开(公告)日：2014-02-18

申请号：US13812867

申请日：2012-08-27

申请人： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/338

CPC分类号： H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。 根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准 的硬掩模和伪栅极，从而提高了器件性能。

公开(公告)号：US20130256808A1

公开(公告)日：2013-10-03

申请号：US13520791

申请日：2012-04-11

申请人： Huaxiang Yin ,  xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236

CPC分类号： H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

摘要翻译： 本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。 根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地 增强了设备的性能，提高了设备​​性能。

公开(公告)号：US20130026496A1

公开(公告)日：2013-01-31

申请号：US13496198

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L29/16 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method for manufacturing a semiconductor device, comprising forming a tunneling dielectric layer, a storage dielectric layer, a gate dielectric layer and a gate layer sequentially on a semiconductor substrate of a first semiconductor material; patterning the tunneling dielectric layer, the storage dielectric layer, the gate dielectric layer and the gate layer to form a gate stack; forming a groove in the semiconductor substrate on the sides of the gate stack; filling the groove with a second semiconductor material different from the first semiconductor material, meanwhile, the entire device is covered by the dielectric layer. The surface energy level in the channel is made to change by the stress generated by the second semiconductor material and the covering dielectric layer, thereby increasing tunneling current and improving the storage efficiency of the device.

摘要翻译： 一种制造半导体器件的方法，包括在第一半导体材料的半导体衬底上依次形成隧道电介质层，存储电介质层，栅极电介质层和栅极层; 图案化隧道介电层，存储介质层，栅极介电层和栅极层以形成栅极堆叠; 在所述半导体衬底的所述栅堆叠的侧面上形成沟槽; 用不同于第一半导体材料的第二半导体材料填充凹槽，同时整个器件被电介质层覆盖。 通过由第二半导体材料和覆盖介电层产生的应力来改变通道中的表面能级，从而增加隧道电流并提高器件的存储效率。

公开(公告)号：US20120181634A1

公开(公告)日：2012-07-19

申请号：US13318344

申请日：2011-04-20

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel. This method has greater process flexibility and simple process complexity with no additional process cost.

摘要翻译： 本发明涉及将应变引入通道的方法和使用该方法制造的器件，该方法包括：提供半导体衬底; 在半导体衬底中形成通道; 在所述通道上形成第一栅介质层; 在所述第一栅极介电层上形成多晶硅栅极层; 将第一元件掺杂或注入到多晶硅栅极层中; 去除所述第一栅极介电层和多晶硅栅极层的一部分，从而形成第一栅极结构; 在通道中形成源极/漏极延伸区域; 在第一栅极结构的两侧形成间隔物; 在通道中形成源极/漏极; 并且进行退火，使得在高温结晶工艺中掺杂或注入第一元素的多晶硅中发生晶格变化，从而在多晶硅栅极层中产生第一应变，并将第一应变通过栅极介电层引入到 这个频道。 该方法具有更大的工艺灵活性和简单的工艺复杂性，无需额外的工艺成本。

公开(公告)号：US09312187B2

公开(公告)日：2016-04-12

申请号：US13520791

申请日：2012-04-11

申请人： Huaxiang Yin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

摘要翻译： 本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。 根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地 增强了设备的性能，提高了设备​​性能。

公开(公告)号：US20150179797A1

公开(公告)日：2015-06-25

申请号：US14355664

申请日：2012-07-03

申请人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

摘要翻译： 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US20150115374A1

公开(公告)日：2015-04-30

申请号：US14387143

申请日：2012-04-26

申请人： Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

摘要翻译： 本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。 因此，本发明还提供了制造半导体结构的方法。 本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

公开(公告)号：US20130137264A1

公开(公告)日：2013-05-30

申请号：US13497526

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Dapeng Chen

IPC分类号： H01L21/306

CPC分类号： H01L21/31053 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823807 ,  H01L29/66545

摘要： A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

摘要翻译： 一种半导体器件制造方法，包括：提供半导体衬底，在所述半导体衬底上设置栅极导体层以及位于所述栅极导体层两侧的源极区域和漏极区域，在所述半导体衬底上形成蚀刻停止层 在蚀刻停止层上形成LTO层，化学机械抛光LTO层，在抛光的LTO层上形成SOG层，形成前金属绝缘层的蚀刻停止层，LTO层和SOG层，背面蚀刻SOG层 和前金属绝缘层的蚀刻停止层，以露出栅极导体层，以及去除栅极导体层。

公开(公告)号：US08384162B2

公开(公告)日：2013-02-26

申请号：US13108742

申请日：2011-05-16

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7845

摘要： The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

摘要翻译： 本发明涉及具有可调节通道应力的装置及其方法。 提供一种包括半导体衬底（202,302）的MOS器件（200,300）。 形成在半导体衬底（202,302）上的沟道; 形成在所述沟道上的栅介质层（204,304）; 形成在栅极介电层（204,304）上的栅极导体（206,306）; 以及形成在闸门两侧的源极和漏极; 其中所述栅极导体（206,306）具有用于产生要施加到所述沟道的第一应力的形状，以便调整所述沟道中的载流子的迁移率。 在本发明中，可以通过控制蚀刻工艺参数来调整栅极导体的形状，从而可以方便地调节通道中的应力，同时可以与产生应力的其他机构组合使用以获得期望的 通道压力。

公开(公告)号：US20130037822A1

公开(公告)日：2013-02-14

申请号：US13394809

申请日：2011-11-25

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/24

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：第一半导体材料的半导体衬底，半导体衬底上的栅极结构，用于产生沟道应力的栅极结构下方的沟道中的晶格位错线，其中晶格位错线与 这个频道。