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185 条记录 (耗时 0.046 秒)

    Silicon-on-insulator ULSI devices with multiple silicon film thicknesses
    31.
    发明授权
    Silicon-on-insulator ULSI devices with multiple silicon film thicknesses 有权
    具有多个硅膜厚度的绝缘体上硅ULSI器件

    公开(公告)号：US07141459B2

    公开(公告)日：2006-11-28

    申请号：US10388297

    申请日：2003-03-12

    申请人： Fu-Liang Yang ,  Hao-Yu Chen ,  Yee-Chia Yeo ,  Carlos H. Diaz ,  Chenming Hu

    发明人： Fu-Liang Yang ,  Hao-Yu Chen ,  Yee-Chia Yeo ,  Carlos H. Diaz ,  Chenming Hu

    IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/36 ,  H01L21/8238

    CPC分类号： H01L21/7624 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of forming a multiple-thickness semiconductor-on-insulator, comprising the following steps. A wafer is provided comprising a semiconductor film (having at least two regions) overlying a buried insulator layer overlying a substrate. The semiconductor film within one of the at least two regions is masked to provide at least one semiconductor film masked portion having a first thickness, leaving exposed the semiconductor film within at least one of the at least two regions to provide at least one semiconductor film exposed portion having the first thickness. In one embodiment, at least a portion of the at least one exposed semiconductor film portion is oxidized to provide at least one partially oxidized, exposed semiconductor film portion. Then the oxidized portion of the exposed semiconductor film is removed to leave a portion of the semiconductor film having a second thickness less than the first thickness.

    摘要翻译： 一种形成多层绝缘体半导体的方法，包括以下步骤。 提供晶片，其包括覆盖在衬底上的掩埋绝缘体层的半导体膜（具有至少两个区域）。 至少两个区域之一内的半导体膜被掩模以提供具有第一厚度的至少一个半导体膜掩模部分，使半导体膜暴露在至少两个区域中的至少一个区域中，以提供至少一个半导体膜暴露 具有第一厚度的部分。 在一个实施例中，所述至少一个暴露的半导体膜部分的至少一部分被氧化以提供至少一个部分氧化的暴露的半导体膜部分。 然后去除暴露的半导体膜的氧化部分，以留下具有小于第一厚度的第二厚度的半导体膜的一部分。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    33.
    发明申请
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US20050272188A1

    公开(公告)日：2005-12-08

    申请号：US11201990

    申请日：2005-08-11

    申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

    CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    Gate electrode for a semiconductor fin device
    34.
    发明申请
    Gate electrode for a semiconductor fin device 有权
    用于半导体鳍片器件的栅电极

    公开(公告)号：US20050233525A1

    公开(公告)日：2005-10-20

    申请号：US10825872

    申请日：2004-04-16

    申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

    摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

    CMOS SRAM cell configured using multiple-gate transistors
    37.
    发明授权
    CMOS SRAM cell configured using multiple-gate transistors 有权
    使用多栅极晶体管配置的CMOS SRAM单元

    公开(公告)号：US06864519B2

    公开(公告)日：2005-03-08

    申请号：US10305728

    申请日：2002-11-26

    申请人： Yee-Chia Yeo ,  Chenming Hu ,  Fu-Liang Yang

    发明人： Yee-Chia Yeo ,  Chenming Hu ,  Fu-Liang Yang

    IPC分类号： H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

    摘要： A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected to a connection linking the respective drain of the N-MGFET of the first pair of N-MGFET to the drain of the P-MGFET of the pair of P-MGFETs; a pair of complementary bit lines, each respectively connected to the source of the N-MGFET of the second pair of N-MGFETS; and a word line connected to the gates of the N-MGFETs of the second pair of N-MGFETs.

    摘要翻译： 由一对P沟道多栅极场效应晶体管（P-MGFET），一对N沟道多栅极场效应晶体管（N）构成的互补金属氧化物半导体静态随机存取存储单元 -MGFET），第二对N-MGFET，其漏极分别连接到将第一对N-MGFET的N-MGFET的相应漏极连接到该对P-MGFET的漏极的连接 -MGFETs 一对互补位线，分别连接到第二对N-MGFETS的N-MGFET的源极; 以及连接到第二对N-MGFET的N-MGFET的门的字线。

    Semiconductor nano-rod devices
    39.
    发明授权
    Semiconductor nano-rod devices 有权
    半导体纳米棒器件

    公开(公告)号：US06855606B2

    公开(公告)日：2005-02-15

    申请号：US10370792

    申请日：2003-02-20

    申请人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hao-Yu Chen ,  Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L29/76 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/784

    CPC分类号： H01L29/7854 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775

    摘要： In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

    摘要翻译： 在制造半导体器件的方法中，半导体层被图案化以在半导体层中形成源极区，沟道区和漏极区。 沟道区域在源极区域和漏极区域之间延伸。 通道区域的角部通过对通道区域进行退火以形成纳米棒结构而变圆。 然后将纳米棒结构的一部分用作栅极通道。 优选地，栅极电介质和栅极电极都围绕纳米杆结构缠绕，栅极电介质位于纳米棒结构和栅电极之间，以形成晶体管器件。

    Contacts to semiconductor fin devices
    40.
    发明授权
    Contacts to semiconductor fin devices 有权
    与半导体鳍片器件接触

    公开(公告)号：US07262086B2

    公开(公告)日：2007-08-28

    申请号：US11478916

    申请日：2006-06-30

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/339

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.

    摘要翻译： 一种用于形成与半导体鳍片的接触的方法，其可以通过首先提供具有顶表面，两个侧壁表面和至少一个端面的半导体鳍片来实现; 形成覆盖鳍片的蚀刻停止层; 形成覆盖所述蚀刻停止层的钝化层; 在所述钝化层中形成暴露所述蚀刻停止层的接触孔; 去除接触孔中的蚀刻停止层; 并用导电材料填充接触孔。