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    Magnetic storage cell memory with back hop-prevention
    31.
    发明授权
    Magnetic storage cell memory with back hop-prevention 有权
    具有防跳跃功能的磁存储单元存储器

    公开(公告)号：US09514796B1

    公开(公告)日：2016-12-06

    申请号：US14751801

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Shigeki Tomishima ,  Wei Wu ,  Shih-Lien Lu ,  James W. Tschanz ,  Georgios Panagopoulos ,  Helia Naeimi

    IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

    Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

    Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路​​，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。

    Encryption code generation using spin-torque NANO-oscillators
    32.
    发明授权
    Encryption code generation using spin-torque NANO-oscillators 有权
    使用自旋转矩NANO振荡器生成加密码

    公开(公告)号：US09369277B2

    公开(公告)日：2016-06-14

    申请号：US14325844

    申请日：2014-07-08

    Applicant: INTEL CORPORATION

    Inventor： Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz

    IPC: H04L9/00 ,  H04L9/08

    CPC classification number: H04L9/0877 ,  G09C1/00 ,  H04L9/0816 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12 ,  H04L2209/24

    Abstract: Embodiments include apparatuses, methods, and systems for generation of an encryption key. In various embodiments, an authentication circuit may include a first bank of spin-torque nano-oscillators (STNOs) including a plurality of STNOs to generate respective oscillation signals and a second bank of STNOs including a plurality of STNOs to generate respective oscillation signals. The authentication circuit may further include a key generation circuit to select a first oscillation signal from the plurality of oscillation signals associated with the first bank of STNOs and a second oscillation signal from the plurality of oscillation signals associated with the second bank of STNOs. The key generation circuit may generate an encryption key based on a frequency of the first oscillation signal and a frequency of the second oscillation signal.

    Abstract translation: 实施例包括用于生成加密密钥的装置，方法和系统。 在各种实施例中，认证电路可以包括包括多个STNO的第一组自旋扭矩纳秒振荡器（STNO）以产生各个振荡信号，以及包括多个STNO的第二组STNO以产生相应的振荡信号。 认证电路还可以包括密钥生成电路，用于从与第一组STNO相关联的多个振荡信号中选择第一振荡信号，以及从与第二组STNO相关联的多个振荡信号中选择第二振荡信号。 密钥生成电路可以基于第一振荡信号的频率和第二振荡信号的频率生成加密密钥。

    All-digital voltage monitor (ADVM) with single-cycle latency
    33.
    发明授权
    All-digital voltage monitor (ADVM) with single-cycle latency 有权

    公开(公告)号：US11211935B2

    公开(公告)日：2021-12-28

    申请号：US17020667

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

    IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

    Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

    Techniques for multi-read and multi-write of memory circuit
    34.
    发明授权
    Techniques for multi-read and multi-write of memory circuit 有权

    公开(公告)号：US11176994B2

    公开(公告)日：2021-11-16

    申请号：US17001432

    申请日：2020-08-24

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

    DISTRIBUTED AND SCALABLE ALL-DIGITAL LOW DROPOUT INTEGRATED VOLTAGE REGULATOR
    35.
    发明申请
    DISTRIBUTED AND SCALABLE ALL-DIGITAL LOW DROPOUT INTEGRATED VOLTAGE REGULATOR 有权

    公开(公告)号：US20210240142A1

    公开(公告)日：2021-08-05

    申请号：US17125768

    申请日：2020-12-17

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

    IPC: G05B11/42 ,  G05F1/46

    Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

    Pre-synaptic learning using delayed causal updates
    37.
    发明授权
    Pre-synaptic learning using delayed causal updates 有权

    公开(公告)号：US10748060B2

    公开(公告)日：2020-08-18

    申请号：US15294666

    申请日：2016-10-14

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

    IPC: G06N3/08 ,  G06N20/00 ,  G06N3/04 ,  G06N3/063

    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

    POST SYNAPTIC POTENTIAL-BASED LEARNING RULE
    39.
    发明申请
    POST SYNAPTIC POTENTIAL-BASED LEARNING RULE 审中-公开

    公开(公告)号：US20180322384A1

    公开(公告)日：2018-11-08

    申请号：US15584510

    申请日：2017-05-02

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Somnath Paul ,  Sadique Ul Ameen Sheik ,  Muhammad M. Khellah

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/04

    Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

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