公开(公告)号：US11790976B2

公开(公告)日：2023-10-17

申请号：US17666452

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C7/10 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F3/0659 ,  G11C7/10 ,  G11C7/1057 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/023 ,  G11C2207/2254

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US11074959B2

公开(公告)日：2021-07-27

申请号：US16741368

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： James A. McCall ,  Christopher P. Mozak ,  Christopher E. Cox ,  Yan Fu ,  Robert J. Friar ,  Hsien-Pao Yang

IPC: G11C11/40 ,  G11C11/4072 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G06F13/16

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

公开(公告)号：US10416912B2

公开(公告)日：2019-09-17

申请号：US15721516

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Christopher P. Mozak ,  Christopher E. Cox

IPC: G06F3/06 ,  G11C11/4076 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

公开(公告)号：US10249351B2

公开(公告)日：2019-04-02

申请号：US15804920

申请日：2017-11-06

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Christopher E. Cox

IPC: G11C16/10 ,  G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C7/22 ,  H04L29/06 ,  G11C11/4093 ,  G11C11/4096 ,  G06K9/00

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

公开(公告)号：US10242727B2

公开(公告)日：2019-03-26

申请号：US15983009

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/409 ,  G11C7/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US20170255412A1

公开(公告)日：2017-09-07

申请号：US15200981

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  James A. McCall

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C2207/2254

Abstract: Examples include techniques for command based on die termination (ODT). In some examples, values are programmed to registers at a memory device to establish one or more internal resistance termination (RTT) settings of ODT at the memory device. Values are also programmed to registers at the memory device to establish one more settings for timing of ODT latency. Programmed values may be changed in order to adjust a signal integrity for the memory device during read or write operations.

公开(公告)号：US09563251B2

公开(公告)日：2017-02-07

申请号：US14142813

申请日：2013-12-28

Applicant: Intel Corporation

Inventor： Saher Abu Rahme ,  Christopher E. Cox ,  Joydeep Ray

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0804 ,  G06F1/3225 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0897 ,  G06F2212/60

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract translation: 具有模式识别机制的高速缓存控制器可以识别高速缓存行中的模式。 代替将高速缓存行的整个数据传送到目的地设备，高速缓存控制器可以生成元信号以表示所识别的位模式。 高速缓存控制器将元信号发送到目的地代替高速缓存行的至少一部分。