公开(公告)号：US20220012187A1

公开(公告)日：2022-01-13

申请号：US17484252

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gustavo K. CONTRERAS MUNOZ ,  Raghunandan MAKARAM ,  George VERGIS

IPC: G06F12/14 ,  G06F21/64 ,  G06F13/42

Abstract: A cryptographic hash based on content of a Sideband Bus Device (SPD) Hub and serial number identifiers for components on a memory module is provided. The cryptographic hash provides the ability to mitigate various supply chain attacks by binding the SPD Hub content to a memory module certificate that is used for authentication. Based on the cryptographic signatures, a certificate is trusted by the platform so the binding of the SPD hub content to the memory module certificate creates a secure way to ensure the components on the memory module have not been tampered with and that the reported attributes of the memory module are correct.

公开(公告)号：US20210313743A1

公开(公告)日：2021-10-07

申请号：US17352211

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R13/633 ,  H01R13/635 ,  H01R12/73

Abstract: Apparatus
An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.

公开(公告)号：US20210151083A1

公开(公告)日：2021-05-20

申请号：US17133484

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Aiswarya M. PIOUS ,  Raji JAMES ,  Phani K. ALAPARTHI ,  George VERGIS ,  Bill NALE ,  Konika GANGULY

IPC: G11C5/14

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

公开(公告)号：US20190139592A1

公开(公告)日：2019-05-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Ge Chang

IPC: G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G06F3/06 ,  G06F13/16

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

公开(公告)号：US20190042500A1

公开(公告)日：2019-02-07

申请号：US16017515

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Bill NALE ,  Chong J. ZHAO ,  James A. McCALL ,  George VERGIS

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

公开(公告)号：US20190042497A1

公开(公告)日：2019-02-07

申请号：US15970639

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  Kenneth FOUST ,  George VERGIS

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G06F13/42 ,  H01R12/72 ,  G11C5/02

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

公开(公告)号：US20180061478A1

公开(公告)日：2018-03-01

申请号：US15282757

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： George VERGIS ,  Kuljit S. BAINS

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

公开(公告)号：US20180004592A1

公开(公告)日：2018-01-04

申请号：US15650479

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS

IPC: G06F11/10 ,  G11C29/44 ,  G11C7/10 ,  G11C29/42 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/10 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

公开(公告)号：US20230017161A1

公开(公告)日：2023-01-19

申请号：US17950663

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/10 ,  G11C8/18

Abstract: System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

公开(公告)号：US20230007775A1

公开(公告)日：2023-01-05

申请号：US17871542

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H05K1/18 ,  H05K1/11

Abstract: Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.