公开(公告)号：US20220129763A1

公开(公告)日：2022-04-28

申请号：US17130661

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sumeet Bandishte ,  Jayesh Gaur ,  Polychronis Xekalakis ,  Ariel Sabba ,  Deborah Marr ,  Sreenivas Subramoney

IPC: G06N5/00 ,  G06N5/04

Abstract: An embodiment of an integrated circuit may comprise a front end unit, and circuitry coupled to the front end unit, the circuitry to provide a high confidence, multiple branch offset predictor. For example, the circuitry may be configured to identify an entry in a multiple-taken-branch prediction table that corresponds to a conditional branch instruction, determine if a confidence level of the entry exceeds a threshold confidence level, and, if so determined, provide multiple taken branch predictions that stem from the conditional branch instruction from the entry in the multiple-taken-branch prediction table. Other embodiments are disclosed and claimed.

公开(公告)号：US20210405896A1

公开(公告)日：2021-12-30

申请号：US17472272

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael D. LeMay ,  Sergej Deutsch ,  Joydeep Rakshit ,  Anant Vithal Nori ,  Jayesh Gaur ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/02

Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a portion of the metadata region, obtain first metadata stored in the metadata region, use the first metadata to determine an alternate memory address in a relocation region, and read, at the alternate memory address, displaced data from the portion of the metadata region included in the address range of the memory allocation. The address range includes one or more bytes of an expected allocation region of the memory allocation.

公开(公告)号：US11043256B2

公开(公告)日：2021-06-22

申请号：US16458022

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Huichu Liu ,  Tanay Karnik ,  Sreenivas Subramoney ,  Jayesh Gaur ,  Sudhanshu Shukla

IPC: G11C11/4096 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/22

Abstract: Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.

公开(公告)号：US20210109839A1

公开(公告)日：2021-04-15

申请号：US17128291

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/24 ,  G06F9/38 ,  G06F15/78

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US10956327B2

公开(公告)日：2021-03-23

申请号：US16457972

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Adithya Nallan Chakravarthi ,  Anant Vithal Nori ,  Jayesh Gaur ,  Sreenivas Subramoney

IPC: G06F12/0815 ,  G06F12/1009

Abstract: Disclosed embodiments relate to systems and methods structured to mitigate cache conflicts through hardware assisted redirection of pages. In one example, a processor includes a translation cache to store a physical to slice mapping in response to a cache conflict mitigation request corresponding to a page; and a cache controller to determine whether the translation cache comprises the physical to slice mapping; determine whether one of a plurality of slices in a translation table comprises the physical to slice mapping if the translation cache does not comprise the physical to slice mapping, the translation table communicably coupled to a non-volatile memory; and if the translation table does not comprise the physical to slice mapping, redirect the cache conflict mitigation request to the non-volatile memory; and allocate a new physical to slice mapping for the page to one of the plurality of slices in the translation table.

公开(公告)号：US20190243760A1

公开(公告)日：2019-08-08

申请号：US16222788

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant V. Nori ,  Sreenivas Subramoney

IPC: G06F12/0811 ,  G06F12/0888 ,  G06F12/0804 ,  G06F12/084 ,  G06F11/34

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US20190243684A1

公开(公告)日：2019-08-08

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

公开(公告)号：US10331582B2

公开(公告)日：2019-06-25

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F13/16 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US20190079877A1

公开(公告)日：2019-03-14

申请号：US15701795

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Sreenivas Subramoney ,  Sanjay Ganapathy

IPC: G06F12/126 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/128

Abstract: In one embodiment, a processor includes: a first cache controller to control a first cache memory. This cache controller may include a replacement circuit to: associate a first priority indicator with a first cache line based on storage of demand data in the first cache line and first learning information associated with a set of demand-based categories of cache lines; and associate a second priority indicator with a second cache line based on storage of prefetch data in the second cache line and second learning information associated with a set of prefetch-based categories of cache lines. Other embodiments are described and claimed.

公开(公告)号：US10176099B2

公开(公告)日：2019-01-08

申请号：US15206589

申请日：2016-07-11

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Supratik Majumder ,  Zvika Greenfield ,  Israel Diamand

IPC: G06F12/0864 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/78 ,  G11C11/406 ,  G06F12/0897

Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.