公开(公告)号：US20180024925A1

公开(公告)日：2018-01-25

申请号：US15214895

申请日：2016-07-20

Applicant: INTEL CORPORATION

Inventor： Raanan Sade ,  Joseph Nuzman ,  Stanislav Shwartsman ,  Igor Yanover ,  Liron Zur

IPC: G06F12/0815 ,  G06F12/0893

CPC classification number: G06F12/0815 ,  G06F12/0833 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.

公开(公告)号：US20180004588A1

公开(公告)日：2018-01-04

申请号：US15708079

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor ,  Joseph Nuzman

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/1064

Abstract: Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.

公开(公告)号：US09858140B2

公开(公告)日：2018-01-02

申请号：US14531498

申请日：2014-11-03

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Raanan Sade ,  Joseph Nuzman

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: Systems and methods for memory corruption detection. An example processing system comprises a processing core including a register to store a base address of a memory corruption detection (MCD) table. The processing core is configured to validate a pointer referenced by a memory access instruction, by comparing a first value derived from a first portion of the pointer to a second value stored in the MCD table at an offset referenced by a second portion of the pointer.

公开(公告)号：US20170185535A1

公开(公告)日：2017-06-29

申请号：US15460977

申请日：2017-03-16

Applicant: INTEL CORPORATION

Inventor： Tomer Stark ,  Ron Gabor ,  Ady Tal ,  Joseph Nuzman

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1425 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/1666 ,  G06F12/0238 ,  G06F2201/80 ,  G06F2212/1032

Abstract: Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.

公开(公告)号：US09619313B2

公开(公告)日：2017-04-11

申请号：US14745172

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Ady Tal ,  Joseph Nuzman

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16

CPC classification number: G06F12/1425 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/1666 ,  G06F12/0238 ,  G06F2201/80 ,  G06F2212/1032

Abstract: Memory corruption detection technologies are described. A processing system can include a processor core including a register to store an address of a memory corruption detection (MCD) table. The processor core can receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory. The memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data. The processor core can retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion. The processor core can send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

公开(公告)号：US20250110876A1

公开(公告)日：2025-04-03

申请号：US18477207

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Ashmita Sinha ,  Joseph Nuzman

IPC: G06F12/0811

Abstract: Techniques for dynamic cache fill prioritization are described. In an embodiment, an apparatus includes a cache at a mid-level of a cache hierarchy; and a mid-level cache (MLC) unit including the cache, a local queue to store MLC lookup requests, an external queue to store MLC fill requests, and an MLC access control hardware. The MLC access control hardware is to dynamically switch prioritization of servicing the MLC lookup requests versus servicing the MLC fill requests.

公开(公告)号：US12135981B2

公开(公告)日：2024-11-05

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11915000B2

公开(公告)日：2024-02-27

申请号：US18160600

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Raanan Sade ,  Liron Zur ,  Igor Yanover ,  Joseph Nuzman

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F11/348

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US11693785B2

公开(公告)日：2023-07-04

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomer Stark ,  Joseph Nuzman

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

CPC classification number: G06F12/0895 ,  G06F9/30043 ,  G06F9/30101 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/1466 ,  G06F2212/7207

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US11645135B2

公开(公告)日：2023-05-09

申请号：US17020663

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/14

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/00 ,  G06F12/109 ,  G06F21/60 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.