公开(公告)号：US20170271448A1

公开(公告)日：2017-09-21

申请号：US15598290

申请日：2017-05-17

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

公开(公告)号：US20160064491A1

公开(公告)日：2016-03-03

申请号：US14937819

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/283 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20240153956A1

公开(公告)日：2024-05-09

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20230111323A1

公开(公告)日：2023-04-13

申请号：US17485325

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rahul RAMAMURTHY ,  Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Inanc MERIC ,  Uygar E. AVCI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/225

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to minimizing sub channel leakage within stacked GAA nanosheet transistors by doping an oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230100952A1

公开(公告)日：2023-03-30

申请号：US17485291

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Ashish Verma PENUMATCHA ,  Seung Hoon SUNG ,  Sarah ATANASOV ,  Jack T. KAVALIEROS ,  Matther V. METZ ,  Uygar E. AVCI ,  Rahul RAMAMURTHY ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.

公开(公告)号：US20220208991A1

公开(公告)日：2022-06-30

申请号：US17695744

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

公开(公告)号：US20220149209A1

公开(公告)日：2022-05-12

申请号：US17580550

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20220093797A1

公开(公告)日：2022-03-24

申请号：US17541199

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Cory C. BOMBERGER ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US20210407999A1

公开(公告)日：2021-12-30

申请号：US16913796

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20200312978A1

公开(公告)日：2020-10-01

申请号：US16363952

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jack KAVALIEROS ,  Ian YOUNG ,  Matthew METZ ,  Uygar AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Seung Hoon SUNG ,  Aditya KASUKURTI ,  Sou-Chi CHANG ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  G09G3/36 ,  G02F1/141 ,  H01L21/28

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.