公开(公告)号：US20150311204A1

公开(公告)日：2015-10-29

申请号：US14739994

申请日：2015-06-15

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L27/0922 ,  H01L21/28185 ,  H01L21/28525 ,  H01L21/28575 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

Abstract translation: 公开了用于形成低接触电阻晶体管器件的技术。 p型锗层设置在p型源极/漏极区及其各自的接触金属之间，n型III-V半导体材料层设置在n型源极/漏极区及其各自的接触金属之间。 n型III-V族半导体材料层可以具有小的带隙（例如，<0.5eV）和/或以其它方式掺杂以提供期望的导电性，并且p型锗层可以例如用硼掺杂。 在III型V材料沉积在n型源极/漏极区域和锗覆盖的p型源极/漏极区域之后，可以执行回蚀工艺以利用n型和p型之间的高度差 区域自对准接触类型，并在p型区域上露出p型锗，并在n型区域上稀薄n型III-V材料。 这些技术可以用于平面和非平面晶体管架构。

公开(公告)号：US20200152635A1

公开(公告)日：2020-05-14

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/45

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066595A1

公开(公告)日：2020-02-27

申请号：US16465490

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  CHYTRA PAWASHE ,  ANAND S. MURTHY ,  DANIEL PANTUSO ,  TAHIR GHANI

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

公开(公告)号：US20200006559A1

公开(公告)日：2020-01-02

申请号：US16024046

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  STEPHEN M. CEA ,  BISWAJEET GUHA ,  TAHIR GHANI ,  WILLIAM HSU

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

公开(公告)号：US20190355721A1

公开(公告)日：2019-11-21

申请号：US16473891

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  SCOTT J. MADDOX ,  RITESH JHAVERI ,  PRATIK A. PATEL ,  SZUYA S. LIAO ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

公开(公告)号：US20190341464A1

公开(公告)日：2019-11-07

申请号：US16416445

申请日：2019-05-20

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/45 ,  H01L29/165 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US20190341300A1

公开(公告)日：2019-11-07

申请号：US16473960

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  BENJAMIN CHU-KUNG ,  SEUNG HOON SUNG ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance.

公开(公告)号：US20190326290A1

公开(公告)日：2019-10-24

申请号：US16465039

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  RISHABH MEHANDRU ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L29/06

Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.

公开(公告)号：US20180108750A1

公开(公告)日：2018-04-19

申请号：US15573168

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  HEI KAM ,  TAHIR GHANI ,  KARTHIK JAMBUNATHAN ,  CHANDRA S. MOHAPATRA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8256 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

公开(公告)号：US20170330955A1

公开(公告)日：2017-11-16

申请号：US15525571

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： NADIA M. RAHHAL-ORABI ,  TAHIR GHANI ,  WILLY RACHMADY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785

Abstract: Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fm.